Packaging substrate, method for manufacturing same, and chip packaging structure having same
A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.
1. A method for manufacturing a packaging substrate comprising:
providing a circuit board, the circuit board comprising a first base having a first surface and a second surface at opposite sides thereof, a first conductive pattern layer formed on the first surface, a second conductive pattern layer formed on the second surface, a first solder mask formed on part of the first surface which is exposed to the first conductive pattern layer and part of the first conductive pattern layer, a second solder mask formed on part of the second surface which is exposed to the second conductive pattern layer and part of the second conductive pattern layer, the first solder mask defining a plurality of first openings and a plurality of second openings, part of the first conductive pattern layer exposed to the first openings and the second openings, the second solder mask defining a plurality of third openings, and part of the second conductive pattern layer exposed to the third openings;
forming a metal layer on the first solder mask;
forming a first plating barrier pattern on the second solder mask and part of the second conductive pattern exposed to the second solder mask;
forming a first plating layer on the metal layer and the first conductive pattern layer;
forming a second plating barrier pattern on the first plating layer, the second plating barrier pattern defining a plurality of first through holes corresponding to the first openings;
forming a first etching barrier pattern on part of the first plating layer which is exposed to the first through holes;
removing the second plating barrier pattern;
forming a second plating layer on the first plating layer and the first etching barrier pattern;
forming a second etching barrier pattern corresponding to the second openings on the second plating layer;
etching the first plating layer and the second plating layer to form a plurality of first conductive posts in the first openings and a plurality of second conductive posts in the second openings.
2. The method of claim 1 , further comprising removing the first plating barrier pattern, the first etching barrier pattern, and the second etching barrier pattern.
3. The method of claim 1 , wherein the first etching barrier pattern is formed on part of the first plating layer which is exposed to the first through holes by a plating method.
4. The method of claim 3 , wherein the first etching barrier pattern is made of tin or nickel.
5. The method of claim 1 , wherein the first etching barrier pattern is molten to form solder caps using an IR-reflow soldering process.