IP Library › Granted Patent US 9,219,001
Granted Patent B2
US 9,219,001 · App. 13/951,793 · Granted Dec 22, 2015

Methods of forming semiconductor devices having recesses

Inventors: Aaron R. Wilson (Boise, ID); Larson Lindholm (Boise, ID); David Hwang (Perrysburg, OH)
Assignee: Micron Technology, Inc.
H01L21/76224H01L29/66795H01L29/7853
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Quick Facts
Patent No.
US 9,219,001
App. No.
13/951,793
Granted
Dec 22, 2015
Kind
B2
Abstract

Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Claims (30)

1. A method for fabricating a semiconductor device, the method comprising:

forming at least two trenches in a substrate through apertures defined in a mask material overlying the substrate;

forming a dielectric material in the at least two trenches;

defining another aperture extending through the mask material and having an upper edge defined at least in part by trenches of the at least two trenches to expose a region of the substrate, the region disposed between two of the at least two trenches; and

forming a recess in the region of the substrate.

2. The method of claim 1 , wherein:

forming a recess in the region of the substrate comprises utilizing portions of the dielectric material as another mask to selectively etch the mask material and the region of the substrate.

3. The method of claim 2 , further comprising removing portions of the dielectric material in the at least two trenches to recess the dielectric material in the at least two trenches relative to a lower recess surface of the recess in the region of the substrate.

4. The method of claim I., wherein forming the at least two trenches comprises forming at least two trenches each defining a trench sidewall and a trench sidewall recess in the trench sidewall.

5. The method of claim 4 , wherein forming a dielectric material in the at least two trenches comprises filling the at least two trenches and the trench sidewall recess of each of the at least two trenches with the dielectric material.

6. The method of claim 5 , wherein forming a recess in the region of the substrate comprises exposing the dielectric material within the trench sidewall recess.

7. A method for fabricating a semiconductor device, the method comprising:

forming a mask material over at least a region of a substrate; and

forming a recess extending through the mask material and in the region of the substrate laterally adjacent to regions of dielectric material to define structures separating the recess from the regions of dielectric material, the recess having an entrance extending between one region of the regions of dielectric material to another region of the regions of dielectric material, the entrance defined at least in part by the mask material.

8. The method of claim 7 , further comprising forming the regions of dielectric material in the substrate, an upper surface of the regions of dielectric material being coplanar with an upper surface of the mask material.

9. The method of claim 7 , further comprising removing the mask material to expose horizontal surfaces of the structures.

10. The method of claim 7 , further comprising removing a portion of the dielectric material to lower an upper surface of the dielectric material relative to the structures.

11. The method of claim 7 , further comprising, after forming the recess, removing a portion of the substrate to enlarge an end of the recess to define an enlarged end protruding at least partially beneath the structures.

12. The method of claim 7 , wherein forming a recess comprises forming a V-shaped recess in the region of the substrate.

13. The method of claim 7 , wherein forming a recess comprises forming a U-shaped recess in the region of the substrate.

14. A method for fabricating a semiconductor device, the method comprising:

forming trenches in a substrate through a mask material;

forming a dielectric material over the mask material and in the trenches to fill the trenches with the dielectric material;

exposing a portion of the mask material through the dielectric material; and

forming a recess in the substrate through the portion of the mask material, leaving at least a remnant portion of the mask material adjacent the recess, the recess defined at least in part by the dielectric material.

15. The method of claim 14 , wherein exposing a portion of the mask material through the dielectric material comprises removing a portion of the dielectric material elevated above the mask material.

16. The method of claim 14 , further comprising removing the mask material to expose structures defined in the substrate between the recess and the trenches.

17. The method of claim 14 , wherein forming a recess comprises forming the recess between sidewalls of the substrate and through the portion of the mask material.

18. The method of claim 14 , wherein forming a recess comprises forming the recess centrally between the trenches.

19. The method of claim 14 , further comprising, after forming the trenches, laterally extending the trenches beneath portions of the substrate.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (4)
Division 13424234 · Mar 19, 2012
Continuation 12944529 · Nov 11, 2010
Division 11778938 · Jul 17, 2007
Related Publication 20130309839A1 · Nov 21, 2013