Vertical NAND device with shared word line steps
A memory device includes a memory cell array having a first side and a second side and a stepped word line contact region located between the first side and the second side of the memory array. A first word line stair pattern is located in the stepped word line contact region adjacent to the first side of the memory array and a second word line stair pattern located in the stepped word line contact region adjacent to the second side of the memory array. A peripheral device region located in the stepped word line contact region between the first and the second word line stair patterns.
1. A memory device, comprising:
a memory cell array having a first side and a second side;
a stepped word line contact region located between the first side and the second side of the memory cell array;
a first word line stair pattern located in the stepped word line contact region adjacent to the first side of the memory cell array;
a second word line stair pattern located in the stepped word line contact region adjacent to the second side of the memory cell array; and
a peripheral device region located in the stepped word line contact region between the first and the second word line stair patterns.
2. The device of claim 1 , wherein a circuit containing peripheral devices in the peripheral device region is electrically connected to word line contacts in both the first word line stair pattern and in the second word line stair pattern.
3. The device of claim 2 , wherein the stepped word line contact region does not contain any dummy word line stair patterns.
4. The device of claim 1 , wherein the device comprises a monolithic three dimensional array of vertical NAND strings.
5. The device of claim 4 , wherein:
the memory cell array comprises the array of vertical NAND strings; and
each vertical NAND string comprises:
a semiconductor channel which extends perpendicular to the major surface of the substrate, wherein a bottom portion of the semiconductor channel contacts the second semiconductor protrusion;
at least one memory film located adjacent to the semiconductor channel; and
a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level.
6. The device of claim 5 , wherein the at least one memory film comprises a blocking dielectric, a charge trapping layer or floating gate, and a tunnel dielectric, and the memory film is located between the semiconductor channel and the plurality of control gate electrodes.