High-K/metal gate stack using capping layer methods, IC and related transistors
Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
1. A method comprising:
providing an implanted substrate with a n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region;
depositing a high dielectric constant (high-k) dielectric layer over the implanted substrate;
forming a first metal having a work function commensurate with a first one of the NMOS region and the PMOS region over the first one of the NMOS and the PMOS regions only, leaving the high-k dielectric layer exposed over a second one of the NMOS and PMOS regions;
depositing a second metal having a work function commensurate with the second one of the NMOS region and the PMOS region over the implanted substrate, wherein a capping layer including a dielectric is deposited over the implanted substrate prior to depositing the second metal, wherein the capping layer is selected from the group consisting of: lanthanum oxide (La 2 O 3 ), dysprosium oxide (DyO), yttrium oxide (Y 2 O 3 ), barium oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO), neodymium oxide (NdO), gadolinium oxide (GdO), and erbium oxide (ErO);
depositing a polysilicon over the implanted substrate; and
patterning to form a first gate stack over the NMOS region and a second gate stack over the PMOS region on the implanted substrate.
2. The method of claim 1 , wherein the capping layer includes a metal selected from the group consisting of: lanthanum (La), dysprosium (Dy), yttrium (Y), strontium (Sr), scandium (Sc), barium (Ba), cerium (Ce), praseodymium (Pr), neodymium (Nd), gadolinium (Gd), and erbium (Er).
3. The method of claim 1 , wherein the high-k dielectric layer is selected from the group consisting of: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), hafnium silicon oxide (HfSiO x ), hafnium aluminum oxide (HfAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), yttrium oxide (Y 2 O 3 ), strontium oxide (SrO) and strontium titanium oxide (SrTiO).
4. The method of claim 1 , wherein the first one of the NMOS and PMOS region is the PMOS region, and the first metal is selected from the group consisting of:
titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
5. The method of claim 1 , wherein the second one of the NMOS and PMOS region is the NMOS region, and the second metal is selected from the group consisting of: titanium nitride (TiN), ruthenium (Ru), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), titanium oxy-nitride (TiON), rhenium (Re), tungsten (W), tantalum silicon nitride (TaSiN), iridium (Ir), nickel silicide (NiSi), iridium silicide (IrSi), niobium (Nb), vanadium (V) and aluminum (Al).
6. A method comprising:
depositing a high dielectric constant (high-k) dielectric layer over an implanted substrate having an n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region;
forming a first metal having a work function commensurate with the NMOS region over the NMOS region only, leaving the high-k dielectric layer exposed over the PMOS region;
depositing a second metal having a work function commensurate with the PMOS region over the implanted substrate, wherein a capping layer including a dielectric is deposited over the implanted substrate prior to depositing the second metal, wherein the capping layer is selected from the group consisting of: lanthanum oxide (La 2 O 3 ), dysprosium oxide (DyO), yttrium oxide (Y 2 O 3 ), barium oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO), neodymium oxide (NdO), gadolinium oxide (GdO), and erbium oxide (ErO);
depositing a polysilicon over the implanted substrate; and
patterning to form a first gate stack over the NMOS region and a second gate stack over the PMOS region on the implanted substrate.
7. The method of claim 6 , wherein the capping layer includes a metal.
8. A method comprising:
depositing a high dielectric constant (high-k) dielectric layer over an implanted substrate having an n-type metal oxide semiconductor (NMOS) region and a p-type metal oxide semiconductor (PMOS) region;
forming a first metal having a work function commensurate with the PMOS region over the PMOS region only, leaving the high-k dielectric layer exposed over the NMOS region;
depositing a second metal having a work function commensurate with the NMOS region over the implanted substrate, wherein a capping layer including a dielectric is deposited over the implanted substrate prior to depositing the second metal, wherein the capping layer is selected from the group consisting of: lanthanum oxide (La 2 O 3 ), dysprosium oxide (DyO), yttrium oxide (Y 2 O 3 ), barium oxide (BaO), strontium oxide (SrO), scandium oxide (ScO), cerium oxide (CeO), praseodymium oxide (PrO), neodymium oxide (NdO), gadolinium oxide (GdO), and erbium oxide (ErO);
depositing a polysilicon over the implanted substrate; and
patterning to form a first gate stack over the NMOS region and a second gate stack over the PMOS region on the implanted substrate.