Receiver deserializer latency trim
A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream. A plurality of storage devices is configured to sample the serial stream. An output demultiplexer is configured to demultiplex the sampled serial stream into a plurality of output streams. A PRBS checker is configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern. A phase rotator is configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver.
1. A receiver, comprising:
an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream;
a plurality of storage devices configured to sample the serial stream;
an output demultiplexer configured to demultiplex the sampled serial stream into a plurality of output streams;
a PRBS checker configured to:
compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern, and generate an error signal bit in response to a discrepancy being detected between the PRBS pattern and the predicted PRBS pattern; and
a phase rotator for reducing latency in the receiver by being configured to:
sequentially reduce skew between a data control clock and a data deserializer clock until the PRBS checker generates the error signal bit based upon the comparison of the PRBS checker, and
adjust the data control clock by a predetermined amount to eliminate the discrepancy.
2. The receiver as recited in claim 1 , further comprising a first cascade of dividers having an inverter at its output to provide the data control clock and a second cascade of dividers to provide the data deserializer clock.
3. The receiver as recited in claim 2 , wherein the PRBS checker is further configured to assess timing between the data control clock and the data deserializer clock.
4. The receiver as recited in claim 2 , wherein the data control clock and the data deserializer clock are initially aligned to be 180 degrees offset.
5. The receiver as recited in claim 1 , wherein the output demultiplexer is clocked according to the data deserializer clock.
6. The receiver as recited in claim 1 , wherein the PRBS checker is further configured to generate the error signal bit until a reset is applied to the PRBS checker, after the phase rotator adjusts data control clock by the predetermined amount.
7. The receiver as recited in claim 1 , further comprising a plurality of latches for each of the plurality of output streams configured to capture the plurality of output streams into a single clock domain.
8. The receiver as recited in claim 1 , further comprising a PRBS generator configured to generate the PRBS.
9. The receiver as recited in claim 1 , wherein the PRBS checker is self-priming.
10. A method for reducing receiver latency, the method comprising:
selecting between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream;
sampling the serial stream using a plurality of storage devices;
demultiplexing the sampled serial stream into a plurality of output streams;
comparing, using a PRBS checker, a PRBS pattern of the plurality of output streams with a predicted PRBS pattern, wherein the PRBS checker is configured to generate an error signal bit in response to a discrepancy being detected between the PRBS pattern and the predicted PRBS pattern;
sequentially reducing skew between a data control clock and a data deserializer clock, using a phase rotator, until the PRBS checker generates the error signal bit based upon the comparing; and
adjusting the data control clock with the phase rotator by a predetermined amount to eliminate the discrepancy.
11. The method as recited in claim 10 , further comprising providing the data control clock using a first cascade of dividers having an inverter at its output and providing the data deserializer clock using a second cascade of dividers.
12. The method as recited in claim 11 , wherein comparing includes assessing timing between the data control clock and the data deserializer clock.
13. The method as recited in claim 11 , wherein the data control clock and the data deserializer clock are initially aligned to be 180 degrees offset.
14. The method as recited in claim 10 , wherein the demultiplexing is clocked according to the data deserializer clock.
15. The method as recited in claim 10 , further comprising applying a reset to the PRBS checker to cancel the error signal bit after adjusting the data control clock by the predetermined amount.
16. The method as recited in claim 10 , further comprising capturing the plurality of output streams into a single clock domain.
17. The method as recited in claim 10 , further comprising generating the PRBS.
18. The method as recited in claim 10 , wherein the PRBS checker is self-priming.