IP Library › Granted Patent US 9,626,325
Granted Patent B2
US 9,626,325 · App. 15/018,376 · Granted Apr 18, 2017

Array processor having a segmented bus system

Inventors: Martin Vorbach (Lingenfeld, DE); Frank May (Munich, DE); Dirk Reichardt (Munich, DE); Frank Lier (Munich, DE); Gerd Ehlers (Grasbrunn, DE); Armin Nückel (Neupotz, DE); Volker Baumgarte (Munich, DE); Prashant Rao (Munich, DE); Jens Oertel (Bad Bergazabern, DE)
Assignee: PACT XPP TECHNOLOGIES AG
G06F13/4027G06F9/3001G06F13/4022G06F15/7825G06F15/80G06F15/8023G06F15/8092G06F15/82
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Quick Facts
Patent No.
US 9,626,325
App. No.
15/018,376
Granted
Apr 18, 2017
Kind
B2
Abstract

An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Claims (10)

1. Apparatus, comprising:

on an integrated circuit chip:

an array of arithmetic processors arranged in a plurality of rows;

a plurality of memory units;

an interface unit;

a bus system comprising segments arranged in a plurality of rows, each segment of a row being selectively connectable to adjacent other segments in a row; each segment providing a plurality of data paths;

a segment of each row being connected to only one arithmetic processor in that same row or to only one memory unit;

wherein a segment that is connected to an arithmetic processor of said plurality of arithmetic processors is not connected to an adjacent arithmetic processor in the same row, but rather is selectively connected an adjacent segment that is in turn connected to said adjacent arithmetic processor in the same row.

2. Apparatus according to claim 1 wherein each segment further comprises one or more protocol lines.

3. Apparatus according to claim 2 , wherein the protocol implemented on said includes ready/ack/rej signals.

Assignments (2)
CHANGE OF NAME Recorded Aug 12, 2021
From: SCIENTIA SOL MENTIS AG
To: PACT XPP SCHWEIZ AG
Reel/Frame 057166/0473 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2018
From: PACT XPP TECHNOLOGIES AG
To: SCIENTIA SOL MENTIS AG
Reel/Frame 045532/0745 →
Priority Claims (16)
WO PCT/EP00/10516 · Oct 9, 2000 · international
DE 101 10 530 · Mar 5, 2001 · national
DE 101 11 014 · Mar 7, 2001 · national
DE 101 35 210 · Jul 24, 2001 · national
DE 101 35 211 · Jul 24, 2001 · national
DE 101 39 170 · Aug 16, 2001 · national
DE 101 42 231 · Aug 29, 2001 · national
DE 101 42 894 · Sep 3, 2001 · national
DE 101 42 903 · Sep 3, 2001 · national
DE 101 42 904 · Sep 3, 2001 · national
DE 101 44 732 · Sep 11, 2001 · national
DE 101 44 733 · Sep 11, 2001 · national
DE 101 45 792 · Sep 17, 2001 · national
DE 101 45 795 · Sep 17, 2001 · national
DE 101 46 132 · Sep 19, 2001 · national
WO PCT/EP01/11299 · Sep 30, 2001 · international
Continuity (7)
Continuation 14718516 · May 21, 2015
Continuation 13903470 · May 28, 2013
Continuation 13289296 · Nov 4, 2011
Continuation 12371040 · Feb 13, 2009
Continuation 10398546
Provisional Application 60238855 · Oct 6, 2000
Related Publication 20160154758A1 · Jun 2, 2016