Proxy wordline stress for read disturb detection
Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.
1. A memory system comprising:
a non-volatile solid state memory comprising selected memory cells coupled to a selected word line, proxy memory cells coupled to a proxy word line, wherein the selected memory cells are non-adjacent to the proxy memory cells; and
a memory controller configured to:
apply a read proxy voltage to the proxy word line when data is read from the selected memory cells; and
determine a read disturb based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.
2. The memory system of claim 1 , wherein the memory controller is further configured to determine that the read disturb is detected if the difference exceeds a threshold value.
3. The memory system of claim 1 , wherein the difference is an error correction code.
4. The memory system of claim 1 , wherein the difference is a number of bits that differ between the predetermined value and the value read from the proxy memory cells.
5. The memory system of claim 1 , wherein the memory controller is further configured to determine the read disturb based additionally on a program and erase cycle count.
6. The memory system of claim 1 , wherein the proxy word line is a last word line in a string to be programmed.
7. The memory system of claim 1 , wherein the proxy word line is a dummy word line.
8. The memory system of claim 1 , wherein the memory controller is further configured to apply a read pass voltage to control gates of transistors in cells that are adjacent to the selected memory cells when the data is read from the selected memory cells, and wherein the read pass voltage is substantially the same as the read proxy voltage.
9. The memory system of claim 1 , wherein the memory controller is further configured to apply a read compare voltage to a control gate of any of the selected memory cells when the data is read from the selected memory cell, wherein the read compare voltage is less than the read proxy voltage.
10. The memory system of claim 1 , wherein the memory controller is further configured to apply the read proxy voltage to the selected word line if a block comprising the selected word line is open, but not if the block comprising the selected word line is closed.
11. The memory system of claim 1 , wherein the difference between the predetermined value stored in the proxy memory cells and the value read from the proxy memory cells is based on a count made during a wear leveling read scan of a number of zeros stored in the proxy memory cells, wherein the proxy word line is a dummy word line, wherein the predetermined value stored in the proxy memory cells is zero, which resulted from erasure of the proxy memory cells, wherein a first block comprises the selected word line, and wherein the memory controller is further configured to copy data from the first block to a second block that has a same cell level as the first block if the number of zeros exceeds a threshold value, or else to copy the data from the first block to a third block having a higher cell level than the first block.
12. The memory system of claim 1 , wherein the difference between the predetermined value stored in the proxy memory cells and the value read from the proxy memory cells is based on a count, which was made prior to a closing of a first block that includes the selected word line, of a number of zeros stored in the proxy memory cells, wherein the proxy word line is a last unprogrammed word line of the first block, wherein the predetermined value is zero and was stored by erasure of the proxy memory cells,
wherein the memory controller is further configured to copy data from the first block to a second block that has a same cell level as the first block if the number of zeros exceeds a threshold value, otherwise to close the first block, wherein the first block is closed if host data is written to the proxy memory cells.
13. The memory system of claim 1 , wherein the memory controller is further configured to apply the read proxy voltage even if a block that includes the selected memory cells is closed, wherein the memory controller is further configured to sample, during a wear leveling read scan, the proxy memory cells for error code correction (ECC), wherein the selected memory cells are included in a first block, wherein the memory controller is further configured to copy data from the first block to a second block that has a same cell level as the first block if the ECC exceeds a threshold value, else fold the data from the first block to a third block having a higher cell level than the first block.
14. A memory device comprising:
a non-volatile solid state memory comprising a selected memory cell coupled to a selected word line, a proxy memory cell coupled to a proxy word line, wherein an unselected memory cell is between the selected memory cell and the proxy memory cell, and the selected memory cell is selected for a read operation, and the proxy memory cell stores a predetermined value instead of host data; and
a means for determining read disturb configured to determine a read disturb based on a difference between the predetermined value stored in the proxy memory cell and a value read from the proxy memory cell, the value read from proxy memory after the read operation completes.
15. The memory device of claim 14 further comprising a means for reading configured to apply a read proxy voltage to the proxy word line only on border word line reads.
16. The memory device of claim 14 further comprising a means for reading configured to apply a read proxy voltage to the proxy word line during the read operation, wherein the read proxy voltage is greater than or equal to a read pass voltage applied to the unselected memory cell during the read operation.
17. The memory device of claim 14 wherein the non-volatile solid state memory comprises single-level cell memory.
18. The memory device of claim 14 wherein the non-volatile solid state memory comprises triple-level cell memory.
19. The memory device of claim 14 further comprising a means for wear leveling configured to determine when to relocate within single-level cell memory and when to move from single-level cell memory to triple-level cell memory or multi-level cell memory.