Semiconductor package, printed circuit board substrate and semiconductor device
A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.
1. A semiconductor device, comprising:
a semiconductor package including a first substrate having a first surface and a second surface, a first wiring formed on the first surface of the first substrate, and a plurality of electrodes formed on the first wiring and electrically connected with the first wiring; and
a second substrate having a first surface facing the first surface of the first substrate, and a second surface, the second substrate including second wirings respectively connected to the plurality of electrodes, the second wirings being formed on the first surface of the second substrate from an inside of a portion facing the semiconductor package to an outside of a periphery of the portion facing the semiconductor package,
wherein, when viewed along a direction perpendicular to the first surface of the first substrate, the first wiring and the second wirings are formed between the electrodes adjacent to each other such that a center of the first wiring and centers of the second wirings deviate from each other.
2. The semiconductor device of claim 1 , wherein between the adjacent electrodes when viewed along the direction perpendicular to the first surface of the first substrate, the first wiring and the second wirings partially overlap.
3. The semiconductor device of claim 2 , wherein between the adjacent electrodes when viewed along the direction perpendicular to the first surface of the first substrate, an area of the first wiring not overlapping with the second wirings is larger than an area of the first wiring overlapping with the second wirings.
4. The semiconductor device of claim 1 , wherein between the adjacent electrodes when viewed along the direction perpendicular to the first surface of the first substrate, the first wiring is interposed between two or more of the second wirings.
5. The semiconductor device of claim 1 , wherein the first wiring and the second wirings are spaced apart from each other when viewed along the direction perpendicular to the first surface of the first substrate.
6. The semiconductor device of claim 5 , wherein between the adjacent electrodes when viewed along the direction perpendicular to the first surface of the first substrate, the first wiring is interposed between two or more second wirings.
7. The semiconductor device of claim 1 , wherein between the adjacent electrodes when viewed along the direction perpendicular to the first surface of the first substrate, a plurality of dummy electrodes, which is physically spaced apart from the first wiring, is formed to overlap with the first wiring.
8. The semiconductor device of claim 7 , wherein an insulating layer is formed between the first wiring and the plurality of dummy electrodes.
9. The semiconductor device of claim 1 , wherein the plurality of electrodes is arranged in a form of a lattice when viewed along the direction perpendicular to the first surface of the first substrate.
10. The semiconductor device of claim 9 , wherein the lattice is one of a square lattice, a rectangular lattice, a triangular lattice and a hexagonal lattice.
11. The semiconductor device of claim 1 , wherein an arrangement pitch rule of the plurality of electrodes is allowed to be alleviated to reduce a chip size of the semiconductor integrated circuit.
12. The semiconductor device of claim 11 , wherein the arrangement pitch rule of the plurality of electrodes is alleviated from 0.5 L to 0.4 L (L is an arbitrary constant).
13. The semiconductor device of claim 11 , wherein the arrangement pitch rule of the plurality of electrodes is alleviated from 0.4 L to 0.3 L (L is an arbitrary constant).
14. The semiconductor device of claim 1 , wherein the electrodes arranged in corners and a central portion of the semiconductor package are not removed so that connectivity with the second substrate is secured.
15. The semiconductor device of claim 1 , wherein a part of distances between adjacent second wirings is same.
16. The semiconductor device of claim 1 , wherein the semiconductor package has a pair of first sides facing each other when viewed along the direction perpendicular to the first surface of the first substrate and a pair of second sides facing each other when viewed along the direction perpendicular to the first surface of the first substrate, the second sides being shorter than the first sides, and
wherein the plurality of electrodes is arranged in a plurality of electrode rows along an elongate direction of the first sides, and in at least two electrode rows, a region where the center of the first wiring and the centers of the second wirings deviate from each other when viewed along the direction perpendicular to the first surface of the first substrate is interposed between the adjacent electrodes.
17. A semiconductor device, comprising:
a semiconductor chip having a first surface and a second surface;
a first layer formed on the first surface and having a plurality of holes;
a plurality of first wirings formed in the plurality of holes;
a plurality of bump electrodes electrically connected with the plurality of first wirings, respectively;
a first insulating layer formed on the first surface;
a second wiring formed on the insulating layer; and
a second insulating layer covering the second wiring,
wherein the second wiring is formed between the plurality of bump electrodes adjacent to each other in a plan view such that centers of the plurality of first wirings and a center of the second wiring are spaced apart from each other when viewed along a direction perpendicular to the first surface.
18. The semiconductor device of claim 17 , wherein at least one of the plurality of first wirings partially overlaps with the second wiring when viewed along a direction perpendicular to the first surface.
19. The semiconductor device of claim 18 , wherein the at least one of the plurality of first wirings is formed between the plurality of bump electrodes adjacent to each other when viewed along a direction perpendicular to the first surface.
20. The semiconductor device of claim 17 , wherein two or more second wirings are formed between the plurality of bump electrodes adjacent to each other when viewed along a direction perpendicular to the first surface.
21. The semiconductor device of claim 17 , wherein the plurality of bump electrodes is arranged in a form of a lattice when viewed along a direction perpendicular to the first surface.
22. The semiconductor device of claim 21 , wherein the lattice is one of a square lattice, a rectangular lattice, a triangular lattice and a hexagonal lattice.