Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices
An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the alternating stack. A backside trench is formed and the sacrificial material layers are replaced with electrically conductive layers. After formation of an insulating spacer in the trench, an epitaxial pedestal structure is grown from a semiconductor portion underlying the backside trench. A source region is formed by introducing dopants into the epitaxial pedestal structure and an underlying semiconductor portion during and/or after epitaxial growth. Alternatively, the backside trench can be formed concurrently with formation of memory openings. An epitaxial pedestal structure can be formed concurrently with formation of epitaxial channel portions at the bottom of each memory opening. After formation and subsequent removal of a dummy trench fill structure in the backside trench, a source region is formed by introducing dopants into the epitaxial pedestal structure.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate;
memory stack structures extending through the alternating stack;
a source region comprising a substrate source portion located in the substrate and an epitaxial pedestal source portion directly contacting a top surface of, and in epitaxial alignment with, the substrate source portion; and
a source contact via structure directly contacting a top surface of the epitaxial pedestal source portion, wherein a sidewall of the epitaxial pedestal source portion forms a straight line with a sidewall of the source contact via structure.
2. The three-dimensional memory device of claim 1 , further comprising:
a backside trench extending through the alternating stack; and
an insulating spacer located in the backside trench and directly contacting the sidewall of the epitaxial pedestal source portion,
wherein the source contact via structure is laterally surrounded by the insulating spacer.
3. The three-dimensional memory device of claim 2 , wherein a bottom surface of the insulating spacer directly contacts a surface of the substrate source portion.
4. The three-dimensional memory device of claim 2 , wherein a horizontal interface between the epitaxial pedestal source portion and the substrate source portion is coplanar with a bottom surface of the insulating spacer.
5. The three-dimensional memory device of claim 2 , wherein the epitaxial pedestal source portion comprises single crystal silicon and the substrate comprises a single crystal silicon wafer or a single crystal silicon layer containing the substrate source portion.
6. The three-dimensional memory device of claim 2 , wherein:
a p-n junction between the source region and a doped semiconductor channel portion within the substrate is spatially offset from an interface between the substrate source portion and the epitaxial pedestal source portion;
a bottom surface of the insulating spacer contacts a top surface of the substrate source portion;
the substrate source portion extends under the insulating spacer to overlap in area, in a view along a direction perpendicular to a top surface of the substrate, a bottom of a source side select gate electrode in the alternating stack; and
the substrate source portion does not extend to a corner of the source side select gate electrode adjacent to the memory stack structure.
7. The three-dimensional memory device of claim 1 , wherein a top surface of the epitaxial pedestal source portion is located above or below a source side select gate electrode in the alternating stack.
8. The three-dimensional memory device of claim 1 , further comprising epitaxial channel portions contacting the substrate and underlying a respective memory stack structure and having a same semiconductor composition as the epitaxial pedestal source portion.
9. The three-dimensional memory device of claim 1 , wherein each of the memory stack structures comprises, from inside to outside:
a semiconductor channel;
a tunneling dielectric layer laterally surrounding the semiconductor channel; and
charge storage regions laterally surrounding the tunneling dielectric layer.
10. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes that are embodied as portions of the electrically conductive layers and have a respective strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level; and
the electrically conductive layers in the stack extend from the device region to a contact region including a plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.
11. The three-dimensional memory device of claim 2 , wherein the insulating spacer directly contacts the sidewall of the source contact via structure.
12. The three-dimensional memory device of claim 2 , wherein the insulating spacer has a uniform thickness along a vertical direction.
13. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers and located over a substrate;
memory stack structures extending through the alternating stack;
a source region comprising a substrate source portion located in the substrate and an epitaxial pedestal source portion directly contacting a top surface of, and in epitaxial alignment with, the substrate source portion;
a backside trench extending through the alternating stack; and
a source contact via structure located in the backside trench and directly contacting a top surface of the epitaxial pedestal source portion and laterally surrounded by an insulating spacer located in the backside trench, wherein a sidewall of the epitaxial pedestal source portion forms a straight line with a sidewall of the source contact via structure.
14. The three-dimensional memory device of claim 13 , wherein the epitaxial pedestal source portion comprises single crystal silicon and the substrate comprises a single crystal silicon wafer or a single crystal silicon layer containing the substrate source portion.
15. The three-dimensional memory device of claim 13 , wherein:
a p-n junction between the source region and a doped semiconductor channel portion within the substrate is spatially offset from an interface between the substrate source portion and the epitaxial pedestal source portion;
a bottom surface of the insulating spacer contacts a top surface of the substrate source portion;
the substrate source portion extends under the insulating spacer to overlap in area, in a view along a direction perpendicular to a top surface of the substrate, a bottom of a source side select gate electrode in the alternating stack; and
the substrate source portion does not extend to a corner of the source side select gate electrode adjacent to the memory stack structure.
16. The three-dimensional memory device of claim 13 , wherein a top surface of the epitaxial pedestal source portion is located above or below a source side select gate electrode in the alternating stack.
17. The three-dimensional memory device of claim 13 , further comprising epitaxial channel portions contacting the substrate and underlying a respective memory stack structure and having a same semiconductor composition as the epitaxial pedestal source portion.
18. The three-dimensional memory device of claim 13 , wherein each of the memory stack structures comprises, from inside to outside:
a semiconductor channel;
a tunneling dielectric layer laterally surrounding the semiconductor channel; and
charge storage regions laterally surrounding the tunneling dielectric layer.
19. The three-dimensional memory device of claim 13 , wherein:
the three-dimensional memory device comprises a vertical NAND device formed in a device region;
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes that are embodied as portions of the electrically conductive layers and have a respective strip shape extending substantially parallel to the top surface of the substrate;
the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level; and
the electrically conductive layers in the stack extend from the device region to a contact region including a plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.