Wiring substrate and manufacturing method of wiring substrate

1. A wiring substrate comprising:

a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern being laminated in this order, the first conductor pattern being divided into a plurality of regions;

a first multilayer wiring layer formed over the first conductor pattern of the laminated sheet, and provided with at least one layer of either one of a first wiring layer and a first insulating layer;

a second multilayer wiring layer formed over the second conductor pattern of the laminated sheet, and provided with at least one layer of either one of a second wiring layer and a second insulating layer;

a first via conductor connecting any of the first wiring layers in the first multilayer wiring layer to the first conductor pattern of the laminated sheet;

a second via conductor connecting any of the second wiring layers in the second multilayer wiring layer to the first conductor pattern of the laminated sheet;

a third via conductor connecting any of the first wiring layers in the first multilayer wiring layer to the second conductor pattern of the laminated sheet; and

a fourth via conductor connecting any of the second wiring layers in the second multilayer wiring layer to the second conductor pattern of the laminated sheet, wherein

the first conductor pattern is interposed between the first via conductor and the second via conductor, and

the second conductor pattern is interposed between the third via conductor and the fourth via conductor.

2. The wiring substrate according to claim 1 , wherein the second conductor pattern has a Young's modulus higher than a Young's modulus of the first conductor pattern.

3. The wiring substrate according to claim 1 , wherein

the first via conductor is electrically connected to a first power supply terminal of a semiconductor element provided over the first conductor pattern,

the second via conductor is electrically connected to a second power supply terminal of a circuit substrate provided over the second conductor pattern,

the third via conductor is electrically connected to a first ground terminal of the semiconductor element, and

the fourth via conductor is electrically connected to a second ground terminal of the circuit substrate.

4. The wiring substrate according to claim 1 , wherein the number of the first wiring layers in the first multilayer wiring layer is less than the number of the second wiring layers in the second multilayer wiring layer.

5. The wiring substrate according to claim 1 , wherein one of the second insulating layers has a Young's modulus higher than each of a Young's modulus of the other second insulating layers,

and the number of the second insulating layers laminated under the one second insulating layer is the same as the number of the first insulating layers on the laminated sheet.

6. The wiring substrate according to claim 1 , further comprising:

a conductor layer formed on the second conductor pattern, wherein the fourth via conductor is connected to the conductor layer.

7. The wiring substrate according to claim 6 , wherein a material of the conductor layer is copper.

8. The wiring substrate according to claim 1 , wherein

a material of the second conductor pattern is nickel, and

a material of the inorganic dielectric layer is any of barium titanate, strontium titanate, lead zirconate titanate, lead lanthanum zirconate titanate, lead niobium zirconate titanate, lead calcium zirconate titanate, lead strontium zirconate titanate, and tantalum oxide.

9. The wiring substrate according to claim 1 , wherein

the second conductor pattern is formed by patterning the conductor layer with a mirror polished surface, and

the inorganic dielectric layer is formed on the surface of the conductor layer.

10. The wiring substrate according to claim 1 , wherein the first conductor pattern, the inorganic dielectric layer, and the second conductor pattern form a capacitor.