Functional core circuitry with serial scan test expected, mask circuitry
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
1. An integrated circuit die comprising:
(a) die input and output pads including a first die input pad and a second die input pad;
(b) a core of functional circuitry having inputs and outputs coupled to the die input and output pads, the core circuitry including:
i. a first core input coupled to the first die input pad, a first core output, a second core input coupled to the second die input pad, and a second core output;
ii. a first scan path having a first scan path input coupled to the first core input and a first scan path output coupled to the first core output;
iii. a second scan path having a second scan path input coupled to the second core input and a second scan path output coupled to the second core output; and
(c) a first test circuit having a first core input coupled to the first core output, a first expected data input coupled to a third die pad, a first mask data input coupled to a fourth die pad, a first scan path input, and a first scan path output;
(d) a second test circuit having a second core input coupled to the second core output, a second expected data input coupled to a fifth die pad, a second mask data input coupled to a sixth die pad, a second scan path input, and a second scan path output; and
(e) a die serial scan path having an input coupled to a die input pad, an output coupled to a die output pad, and being connected in series with the first scan path input, the first scan path output, the second scan path input, and the second scan path output.
2. The integrated circuit die of claim 1 in which the die includes a first buffer coupling the first die input pad to the first core input, and a second buffer coupling the second die input pad to the second core input.
3. The integrated circuit die of claim 1 in which the first expected data input and second expected data input are separate from one another.
4. The integrated circuit die of claim 1 in which the first mask data input and second mask data input are separate from one another.
5. The integrated circuit die of claim 1 in which the die includes a first buffer coupling the input of the die serial scan path to a die input pad.
6. The integrated circuit die of claim 1 in which the first scan path, the second scan path, and the die serial scan path are separate from one another.