Series resistance reduction in vertically stacked silicon nanowire transistors
Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.
1. A method of fabricating a portion of a nanowire field effect transistor (FET), the method comprising:
forming a sacrificial layer and a nanowire layer;
forming a spacer around portions of the sacrificial layer and the channel nanowire layer;
removing selected portions of the sacrificial layer and the nanowire layer that are not under the spacer such that a sidewall portion of the sacrificial layer and a sidewall portion of the nanowire layer are exposed;
selectively removing a portion of the sidewall portion of the sacrificial layer;
forming a diffusion block in a space that was occupied by the removed portion of the sidewall portion of the sacrificial layer;
forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region;
converting a portion of the sidewall portion of the nanowire layer to a source extension region or a drain extension region; and
removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region;
wherein converting the sidewall portion of the nanowire layer to the source extension region or the drain extension region comprises implanting dopant to the source region or the drain region to form at least one junction.
2. The method of claim 1 , wherein the sacrificial layer removal process comprises a wet process.
3. The method of claim 2 , wherein a selectivity of the wet process to the diffusion block is below a predetermined threshold.
4. The method of claim 2 , wherein the wet process comprises an etch.
5. The method of claim 1 , wherein the sacrificial layer removal process comprises a reactive ion etch.
6. The method of claim 5 , wherein the reactive ion etch causes an etch rate of the diffusion block that is below a predetermined threshold.
7. The method of claim 1 , wherein the forming of the sacrificial layer and the nanowire layer comprises forming a stack comprising alternating sacrificial layers and nanowire layers.
8. The method of claim 1 further comprising:
forming a gate region around the nanowire layer;
wherein the gate region controls a flow of current from the source region through the nanowire layer into the drain region.
9. The method of claim 1 , wherein the at least one junction comprises an extension junction of the nanowire layer.