IP Library Granted Patent US 10,249,523
Granted Patent B2
US 10,249,523 · App. 15/135,022 · Granted Apr 2, 2019

Overlay and semiconductor process control using a wafer geometry metric

Inventors: Pradeep Vukkadala (Newark, CA); Sathish Veeraraghavan (Santa Clara, CA); Jaydeep K. Sinha (Livermore, CA)
Assignee: KLA-Tencor Corporation
H01L21/67288G01B9/02021G01B9/02027G01B9/02057G01B11/161G01B11/2441G01B11/272G03F7/70633G03F7/70783H01L21/67271H01L22/12H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,249,523
App. No.
15/135,022
Granted
Apr 2, 2019
Kind
B2
Abstract

The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.

Claims (34)

1. A method for sorting wafers utilizing a slope of shape metric, comprising:

receiving a plurality of wafers;

acquiring a set of wafer shape values from a surface of each wafer at a selected process level;

generating a set of residual slope shape metrics for each wafer by calculating a residual slope shape metric at each of a plurality of points of each wafer;

determining a neutral surface of each wafer in a chucked state;

calculating a neutral surface factor (NSF) for each wafer utilizing the determined neutral surface for each wafer and a plurality of positions associated with a plurality of patterns of each wafer;

determining a set of pattern placement error (PPE) residual values for each wafer, the PPE residual value for each point for each wafer being a product of at least the calculated NSF for each wafer, the residual slope shape metric for the point, and a thickness of the wafer;

determining one or more thresholds for the set of residual shape metrics suitable for maintaining the set of PPE residuals below one or more selected levels;

monitoring each of the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer; and

modifying one or more wafer fabrication processes, responsive to the monitoring of each of the plurality of wafers, in order to maintain the generated set of residual slope shape metrics for each wafer below the one or more thresholds.

2. The method of claim 1 , wherein the NSF is a distance between the neutral surface and a pattern surface of the wafer.

3. The method of claim 1 , wherein the selected process level is a bare wafer process level.

4. The method of claim 1 , wherein the characterizing the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer comprises:

sorting the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer.

5. The method of claim 4 , wherein the sorting the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer comprises:

binning each wafer according to a comparison between the set of residual shape metrics associated with the wafer and the determined threshold.

6. The method of claim 1 , further comprising:

responsive to the monitoring of each of the plurality of wafers, identifying one or more processes in order to establish the generated set of residual slope shape metrics for each wafer below the one or more thresholds.

7. A system for sorting wafers utilizing a slope of shape metric, comprising:

a topography system configured to perform a set of topography measurements in order to acquire a set of wafer shape values, at a selected process level, from a surface of each wafer of a plurality of wafers; and

one or more computing systems communicatively coupled to the topography and configured to receive the set of topography measurements, the one or more computing systems further configured to:

generate a set of residual slope shape metrics for each wafer by calculating a residual slope shape metric at each of a plurality of points of each wafer;

determine a neutral surface of each wafer in a chucked state;

calculate a neutral surface factor (NSF) for each wafer utilizing the determined neutral surface for each wafer and a plurality of positions associated with a plurality of patterns of each wafer;

determine a set of pattern placement error (PPE) residual values for each wafer, the PPE residual value for each point for each wafer being a product of at least the calculated NSF for each wafer, the residual slope shape metric for the point, and a thickness of the wafer;

determine one or more thresholds for the set of residual shape metrics suitable for maintaining the set of PPE residuals below one or more selected levels;

monitor each of the plurality of wafers by comparing the determined one or more thresholds for the set of residual shape metrics to the generated set of residual slope shape metrics for each wafer; and

modify one or more wafer fabrication processes, responsive to the monitoring of each of the plurality of wafers, in order to maintain the generated set of residual slope shape metrics for each wafer below the one or more thresholds.

8. The system of claim 7 , wherein the topography systems comprises:

an interferometry based topography system.

9. The system of claim 7 , wherein the interferometry based topography system comprises:

a dual Fizeau interferometer.

10. The system of claim 7 , wherein the topography systems comprises:

a topography system configured to measure a front-side surface of the wafer and the back-side surface of the wafer simultaneously.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2018
From: VUKKADALA, PRADEEP; VEERARAGHAVAN, SATHISH; SINHA, JAYDEEP K.
To: KLA-TENCOR CORPORATION
Reel/Frame 046027/0106 →
Continuity (3)
Continuation 13476328 · May 21, 2012
Provisional Application 61545942 · Oct 11, 2011
Related Publication 20160372353A1 · Dec 22, 2016
Cited By (5)
US 12,197,137 US 12,481,223 US 12,644,696 US 12,645,152 US 12,674,662