Semiconductor device
View Patent ↗The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented.
1. A semiconductor device comprising:
a substrate;
a first oxide semiconductor layer comprising at least one of indium, gallium, and zinc over the substrate;
a second oxide semiconductor layer comprising at least one of indium, gallium, and zinc;
a source electrode layer and a drain electrode layer each electrically connected to the first oxide semiconductor layer;
a gate insulating layer over the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and
a gate electrode over the gate insulating layer,
wherein the first oxide semiconductor layer comprises a first channel formation region and a second channel formation region,
wherein the second oxide semiconductor layer comprises a first surface parallel to a top surface of the substrate,
wherein the first surface of the second oxide semiconductor layer is between the first channel formation region and the second channel formation region of the first oxide semiconductor layer, and
wherein a bottom surface of the gate insulating layer is in direct contact with the first surface of the second oxide semiconductor layer.
2. The semiconductor device according to claim 1 ,
wherein the second oxide semiconductor layer is in direct contact with a top surface of the source electrode layer and the drain electrode layer.
3. The semiconductor device according to claim 1 ,
wherein the first oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein the second oxide semiconductor layer comprises indium, gallium, and zinc.
4. The semiconductor device according to claim 1 , wherein an end portion of the first oxide semiconductor layer, and an end portion of the second oxide semiconductor layer are aligned with each other when seen from a direction perpendicular to a top surface of the second oxide semiconductor layer.
5. The semiconductor device according to claim 1 ,
wherein the source electrode layer is in direct contact with a side surface of the first oxide semiconductor layer, and
wherein the drain electrode layer is in direct contact with a side surface of the first oxide semiconductor layer.
6. The semiconductor device according to claim 1 , further comprising:
a base insulating layer below the first oxide semiconductor layer and over the substrate,
wherein the base insulating layer comprises oxygen, and
wherein the base insulating layer is configured to supply a part of the oxygen to the first oxide semiconductor layer.
7. A semiconductor device comprising:
a first oxide semiconductor layer comprising at least one of indium, gallium, and zinc;
a second oxide semiconductor layer comprising at least one of indium, gallium, and zinc;
a source electrode layer and a drain electrode layer each electrically connected to the first oxide semiconductor layer;
a gate insulating layer over the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and
a gate electrode over the gate insulating layer,
wherein the first oxide semiconductor layer comprises a first channel formation region, a second channel formation region, a first region, and a second region,
wherein the first region is in direct contact with a first side surface, which extends in a plane perpendicular to a channel length direction, of the first channel formation region and a first side surface, which extends in the plane perpendicular to the channel length direction, of the second channel formation region,
wherein the second region is in direct contact with a second side surface, which extends in a plane perpendicular to the channel length direction, of the first channel formation region and a second side surface, which extends in the plane perpendicular to the channel length direction, of the second channel formation region,
wherein the gate electrode overlaps with the first channel formation region, the second channel formation region, and the first region and the second region of the first oxide semiconductor layer, and
wherein the second oxide semiconductor layer is in direct contact with a top surface of the source electrode layer and the drain electrode layer.
8. The semiconductor device according to claim 7 ,
wherein the first oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein the second oxide semiconductor layer comprises indium, gallium, and zinc.
9. The semiconductor device according to claim 7 , wherein an end portion of the first oxide semiconductor layer, and an end portion of the second oxide semiconductor layer are aligned with each other when seen from a direction perpendicular to a top surface of the second oxide semiconductor layer.
10. The semiconductor device according to claim 7 ,
wherein the source electrode layer is in direct contact with a side surface of the first region of the first oxide semiconductor layer, and
wherein the drain electrode layer is in direct contact with a side surface of the second region of the first oxide semiconductor layer.
11. The semiconductor device according to claim 7 , further comprising:
a base insulating layer below the first oxide semiconductor layer,
wherein the base insulating layer comprises oxygen, and
wherein the base insulating layer is configured to supply a part of the oxygen to the first oxide semiconductor layer.