Skew compensation for multi-domain clock generation

1. A circuit including multiple clock domains, comprising

clock circuitry to provide at least first and second domain clocks each domain clock based on an input clock with an input clock frequency, and each domain clock generated with randomization, the domain clocks having a relative clock skew;

a first circuit in a first clock domain is configured for operation with the first domain clock, and includes

a first free-running counter with a defined first selected roll-over count, to generate a first free-running count (N 1 ( k )) based on the first domain clock; and

a second circuit in a second clock domain is configured for operation with the second domain clock, and includes

a second free-running counter with a defined second selected roll-over count, to generate a second free-running count (N 2 ( k )) based on the second domain clock.

2. The circuit of claim 1 , wherein:

the first and second domain clocks are randomized by dithering.

3. The circuit of claim 1 , further comprising:

skew compensation circuitry operable

at a selected start time, to store first and second initial counter values (N 1 ( 0 ) and N 2 ( 0 )) respectively for the first and second free-running counters; and

at a selected cross-domain event time associated with a cross-domain event, to read the first and second counter values N 1 ( k ) and N 2 ( k ); and

to determine a clock skew condition of the first and second domain clocks based on N 1 ( 0 ) and N 2 ( 0 ), and N 1 ( 1 ) and N 2 ( 1 ).

4. The circuit of claim 3 , wherein:

for the clock skew condition, N 1 ( k )−N 2 ( k ) is different than N 1 ( 0 )−N 2 ( 0 ) by a defined amount.

5. The circuit of claim 3 , wherein:

the first circuit includes a first memory, and the second circuit includes a second memory; and

the cross-domain event is reading data from the first and second memories.

6. The circuit of claim 5 , wherein:

compensating for clock skew is accomplished by adjusting memory pointers for reading data from the first and second memories.

7. The circuit of claim 1 , wherein

a frequency of at least one of the domain clocks is based on a multiplication or division of the input clock frequency.

8. A circuit including multiple clock domains for use in a system for radio frequency (RF) communications, comprising

TX (transmit) signal path circuitry to receive digital TX baseband signals, and configured

to capture, into a TX capture memory, TX data including phase data related to the TX baseband signals,

to perform QMC filtering for quadrature mismatch compensation (QMC) to generate QMC pre-compensated TX baseband signals, and

to generate, based on the QMC pre-compensated TX baseband signals, TX/RF signals;

FBRX (feedback receive) signal path circuitry, to selectively receive the QMC pre-compensated TX/RF signals as feedback FBRX/RF signals, and configured to generate, from the FBRX/RF signals, feedback digital FBRX baseband signals, and

to capture, into a RX capture memory, FBRX data including phase data related to the FBRX baseband signals;

the TX signal path circuitry including QMC circuitry to receive the TX baseband signals and perform the QMC filtering to generate the pre-compensated TX baseband signal; and

multi-domain clock generation circuitry including at least a TX domain clock generator to generate for the TX signal path circuitry a TX domain clock, and a FBRX domain clock generator to generate for the FBRX signal path circuitry a FBRX domain clock, each domain clock based on an input global clock with an input global clock frequency, and each domain clock generated with randomization, the TX and FBRX domain clocks having a relative clock skew:

the TX domain clock generator including a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N 1 ( k )) based on the TX domain clock; and

the FBRX domain clock generator including a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N 2 ( k )) based on the FBRX domain clock.

9. The circuit of claim 8 , wherein:

the TX and FBRX domain clocks are randomized by dithering.

10. The circuit of claim 8 , further comprising:

skew compensation circuitry operable

at a selected start time, to store first and second initial counter values (N 1 ( 0 ) and N 2 ( 0 )) respectively for the first and second free-running counters; and

at a selected cross-domain event time associated with a cross-domain event, to read the first and second counter values N 1 ( k ) and N 2 ( k ); and

to determine a clock skew condition of the TX and FBRX domain clocks based on N 1 ( 0 ) and N 2 ( 0 ), and N 1 ( 1 ) and N 2 ( 1 ).

11. The circuit of claim 10 , wherein:

for the clock skew condition, N 1 ( k )−N 2 ( k ) is different than N 1 ( 0 )−N 2 ( 0 ) by a defined amount.

12. The circuit of claim 10 , wherein:

the TX signal path circuitry includes a first memory, and the FBRX signal path circuitry includes a second memory; and

the cross-domain event is reading data from the first and second memories.

13. The circuit of claim 12 , wherein:

compensating for clock skew is accomplished by adjusting memory pointers for reading data from the first and second memories.

14. The circuit of claim 8 , wherein

a frequency of at least one of the TX and FBRX domain clocks is based on a multiplication or division of the input clock frequency.

15. The circuit of claim 8 , further comprising

a QMC adaptation engine coupled to the TX and FBRX memories, and configured to adapt QMC filter coefficients, which are used for QMC filtering, using the TX and FBRX data captured into the TX and FBRX capture memories.

16. A method of multi-domain clock generation useable in a system with multiple clock domains, the method comprising

generating at least first and second domain clocks, each domain clock based on an input clock with an input clock frequency, and each domain clock randomized, the domain clocks having a relative clock skew;

supplying the first domain clock to a first clock domain, the first clock domain including a first free-running counter with a defined first selected roll-over count, to generate a first free-running count (N 1 ( k )) based on the first domain clock; and

supplying the second domain clock to a second clock domain, the second clock domain including a second free-running counter with a defined second selected roll-over count, to generate a second free-running count (N 2 ( k )) based on the second domain clock.

17. The method of claim 16 , further comprising:

at a selected start time, storing first and second initial counter values (N 1 ( 0 ) and N 2 ( 0 )) respectively for the first and second free-running counters; and

at a selected cross-domain event time associated with a cross-domain event, reading the first and second counter values N 1 ( k ) and N 2 ( k ); and

determining a clock skew condition of the first and second domain clocks based on N 1 ( 0 ) and N 2 ( 0 ), and N 1 ( 1 ) and N 2 ( 1 ).

18. The method of claim 17 , wherein:

for the clock skew condition, N 1 ( k )−N 2 ( k ) is different than N 1 ( 0 )−N 2 ( 0 ) by a defined amount.

19. The method of claim 17 , wherein:

the cross-domain event is reading data from a first domain data capture memory, and a second domain data capture memory.

20. The circuit of claim 19 , wherein:

compensating for clock skew is accomplished by adjusting memory pointers for reading data from the first and second domain capture memories.