Secondary phase compensation assist for PLL IO delay aligning sync signal to system clock signal
A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.
1. A method of operating a network device comprising:
receiving a first counter synchronization signal that was transmitted across a backplane;
receiving a first system clock signal that was transmitted across the backplane;
generating a second counter synchronization signal indicating when to update a counter local to the network device;
feeding back the second counter synchronization signal as a counter synchronization feedback signal;
determining a time difference between a transition of the first counter synchronization signal and a transition of the counter synchronization feedback signal; and
adjusting a timing of the second counter synchronization signal based on the time difference.
2. The method of claim 1 further comprising:
generating a second system clock signal in a phase-locked loop; and
generating the second counter synchronization signal by dividing the second system clock signal.
3. The method of claim 2 further comprising:
adjusting a divide value of a divider circuit to adjust the timing of the second counter synchronization signal based on the time difference;
determining a residue of the time difference according to a remaining time difference not accounted for by adjusting the divide value; and
adjusting the phase-locked loop based on the residue as part of adjusting the timing of the second counter synchronization signal.
4. The method of claim 2 wherein adjusting the timing of the second counter synchronization signal includes:
making a coarse adjustment based on the time difference, the coarse adjustment being a change to a divide value used to generate the second counter synchronization signal by dividing the second system clock signal;
determining a residue based on a remaining time difference after the coarse adjustment; and
making a fine adjustment based on the residue by adjusting the phase-locked loop.
5. The method of claim 4 further comprising making the fine adjustment in a plurality of steps.
6. The method of claim 4 further comprising making the fine adjustment by adjusting a feedback divider divide value in a feedback divider of the phase-locked loop.
7. The method of claim 1 further comprising:
generating a first time stamp based on the transition of the first counter synchronization signal;
generating a second time stamp based on the transition of the counter synchronization feedback signal;
generating a plurality of third time stamps corresponding to respective edges of the first system clock signal;
determining a closest one of the plurality of third time stamps to the second time stamp; and
generating the time difference by determining a difference between the first time stamp and the closest one of the plurality of third time stamps.
8. The method of claim 1 further comprising:
after adjusting the timing of the second counter synchronization signal based on the time difference, waiting for a predetermined time period; and
responsive to an end of the predetermined time period, readjusting the timing of the second counter synchronization signal based a newly determined time difference between a transition of a later counter synchronization feedback signal and another edge of the first system clock signal.
9. The method of claim 1 wherein the counter local to the network device is a time of day counter.
10. The method of claim 1 further comprising adjusting the timing of the second counter synchronization signal based on the time difference to obtain a zero delay second counter synchronization signal.
11. A network timing device comprising:
a first input terminal to receive a first counter synchronization signal from a backplane;
a second input terminal to receive a first system clock signal from the backplane;
timing circuitry configured to generate a second system clock signal and a second counter synchronization signal based on the first system clock signal;
a third input terminal coupled to receive the second counter synchronization signal as a counter synchronization feedback signal; and
control logic configured to: determine a time difference between a transition of the first counter synchronization signal and a transition of the counter synchronization feedback signal; and adjust a timing of the second counter synchronization signal based on the time difference.
12. The network timing device of claim 11 wherein the timing circuitry includes a phase-locked loop and a divider circuit.
13. The network timing device of claim 12 further comprising:
a first time stamper to provide a first time stamp indicative of the transition of the first counter synchronization signal;
a second time stamper to generate second time stamp indicative of the transition of the counter synchronization feedback signal;
a third time stamper to generate a plurality of third time stamps corresponding to edges of the first system clock signal, the time difference based on a difference between the first time stamp and one of the plurality of third time stamps.
14. The network timing device of claim 12 wherein the control logic is further configured to:
determine an adjustment to a divide value of the divider circuit to adjust the timing of the second counter synchronization signal based on the time difference; and
to determine a residue of the time difference after the adjustment to the divide value is determined.
15. The network timing device of claim 14 wherein the control logic is configured to adjust the phase-locked loop based on the residue as part of adjusting the timing of the second counter synchronization signal.
16. The network timing device of claim 12 wherein the control logic is further configured to:
determine a coarse adjustment to the timing of the second counter synchronization signal based on the time difference, the coarse adjustment being a change to a divide value used in the divider circuit to generate the second counter synchronization signal; and
determine a fine adjustment according to a residue based on a remaining time difference between the first system clock signal and the second counter synchronization signal after the coarse adjustment.
17. The network timing device of claim 16 wherein the fine adjustment is made to the phase-locked loop in multiple steps.
18. The network timing device of claim 16 wherein the fine adjustment is made by adjusting a divide value of a feedback divider of the phase-locked loop.
19. The network timing device of claim 11 wherein the control logic is configured to adjust the timing of the second counter synchronization signal based on the time difference such that subsequent time differences between subsequent transitions of the second counter synchronization signal and subsequent corresponding edges of the first system clock signal are substantially zero.
20. A network timing system comprising:
a backplane;
a plurality of network timing devices coupled to the backplane; and
a first network timing device of the plurality of network timing devices configured to receive a first counter synchronization signal and a first system clock signal from the backplane, the first network timing device including timing circuitry configured to generate a second system clock signal and a second counter synchronization signal based on at least the first system clock signal, the first network timing device further including control logic configured to determine a time difference between a transition of the first counter synchronization signal and a transition of a feedback version of the second counter synchronization signal, and adjust a timing of the second counter synchronization signal based on the time difference.