IP Library Granted Patent US 12,206,752
Granted Patent B2
US 12,206,752 · App. 17/986,714 · Granted Jan 21, 2025

Data protocol over clock line

Inventor: Vivek Sarda (Austin, TX)
Assignee: Skyworks Solutions, Inc.
H04L7/0008H04L7/0079H04L7/0091H04L63/0428H04L67/147
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,206,752
App. No.
17/986,714
Granted
Jan 21, 2025
Kind
B2
Abstract

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

Claims (27)

1. A method of synchronizing devices, the method comprising:

sending a sequence from a first device to a plurality of receiving devices over a clock signal line to identify a beacon is coming;

sending the beacon to a plurality of receiving devices over the clock signal line;

sending at least a first control word on the clock signal line after sending the beacon, the first control word including a length field to specify a first length of first data to follow the first control word;

sending at least a second control word on the clock signal line before a next beacon is transmitted, the second control word including a second length field to specify a second length of data to follow the second control word; and

controlling a clock signal on the clock signal line to have different duty cycles based at least in part on information sent over the clock signal line.

2. The method of claim 1 further comprising sending the beacon by pulse width modulating the clock signal on the clock signal line.

3. The method of claim 1 further comprising sending the first control word by pulse width modulating a clock signal on the clock signal line.

4. The method of claim 1 wherein the first control word further includes an encryption field.

5. The method of claim 4 further comprising enabling the encryption field and sending encrypted time of day information on the clock signal.

6. The method as recited in claim 1 further comprising one or more of the plurality of receiving devices sending a message to a first device regarding status of receipt of the data.

7. The method as recited in claim 1 wherein the first data includes an embedded time of day value that corresponds to the beacon, a previous beacon, or a subsequent beacon.

8. The method as recited in claim 1 wherein the first control word includes an error detection or correction field.

9. The method as recited in claim 8 wherein the plurality of receiving devices perform error detection or correction of the data received on the clock signal when the error detection or correction field is enabled.

10. The method as recited in claim 1 wherein the first control word includes a field that indicates whether the first control word is extended.

11. An apparatus comprising:

a plurality of receiving devices in communication with a clock signal line; and

a timing card having a pulse width modulation circuit that modulates periods of a clock signal to generate a pulse width modulated clock signal that contains a sequence that identifies a beacon is coming, the pulse width modulation circuit further sends at least a first control word on the clock signal line, the first control word including a first length field to specify a first length of data to follow the first control word, the pulse width modulation circuit sends at least a second control word on the clock signal line before a next beacon is transmitted, the second control word including a second length field to specify a second length of data to follow the second control word, and the pulse width modulation circuit further identifies whether the pulse width modulated clock signal on the clock signal line has different duty cycles based at least in part on information sent over the clock signal line.

12. The apparatus of claim 11 wherein the sequence that identifies the beacon is coming has a plurality of 25% duty cycle signals.

13. The apparatus of claim 12 wherein the pulse width modulation circuit modulates periods of the clock signal to generate the first control word.

14. The apparatus of claim 11 wherein the first control word further includes an encryption field.

15. The apparatus of claim 14 further comprising enabling the encryption field and sending encrypted time of day information on the clock signal.

16. The apparatus as recited in claim 11 further comprising one or more of the plurality of receiving devices sending a message to a first device regarding status of receipt of the data.

17. The apparatus as recited in claim 11 wherein the first length of data includes a time of day value that corresponds to the beacon, a previous beacon, or a subsequent beacon.

18. The apparatus as recited in claim 11 wherein the first control word includes an error detection or correction field.

19. The apparatus as recited in claim 18 wherein the plurality of receiving devices perform error detection or correction of the data received on the clock signal when the error detection or correction field is enabled.

20. The apparatus as recited in claim 11 wherein the first control word includes a field that indicates whether the first control word is extended.

Continuity (2)
Continuation 17375634 · Jul 14, 2021
Related Publication 20230224137A1 · Jul 13, 2023
References Cited (104)
US 5140611A · Jones et al. · 1992 [cited by applicant]
US 5509038A · Wicki · 1996 [cited by applicant]
US 5644604A · Larson · 1997 [cited by applicant]
US 5964880A · Liu · 1999 [cited by applicant]
US 6549046B1 · Klecka, III · 2003 [cited by applicant]
US 6760586B1 · Lee · 2004 [cited by applicant]
US 6839858B1 · James · 2005 [cited by applicant]
US 6885647B1 · Chung et al. · 2005 [cited by applicant]
US 7002996B1 · Dougherty et al. · 2006 [cited by applicant]
US 7079589B1 · Maksimovic et al. · 2006 [cited by applicant]
US 7116743B1 · Wang · 2006 [cited by applicant]
US 7203227B1 · Currivan · 2007 [cited by applicant]
US 7417510B2 · Huang · 2008 [cited by applicant]
US 7451337B1 · Hewitt · 2008 [cited by applicant]
US 7451339B2 · Smith, Sr. · 2008 [cited by applicant]
US 7535893B1 · Beladakere et al. · 2009 [cited by applicant]
US 7860205B1 · Aweya et al. · 2010 [cited by applicant]
US 7903681B2 · Roberts et al. · 2011 [cited by applicant]
US 8355476B2 · Lee · 2013 [cited by applicant]
US 8942561B2 · Boyd et al. · 2015 [cited by applicant]
US 8989328B2 · Wong · 2015 [cited by examiner]
US 9246615B2 · Ellegard et al. · 2016 [cited by applicant]
US 9369270B1 · Spijker · 2016 [cited by applicant]
US 9426762B2 · Ehlers et al. · 2016 [cited by applicant]
US 9479182B1 · Baidas et al. · 2016 [cited by applicant]
US 9594396B2 · Turner et al. · 2017 [cited by applicant]
US 9628255B1 · Baidas · 2017 [cited by examiner]
US 9665121B2 · Aweya · 2017 [cited by applicant]
US 9860004B2 · Joergensen · 2018 [cited by applicant]
US 9960873B2 · Yang · 2018 [cited by applicant]
US 10007639B2 · Mitric · 2018 [cited by applicant]
US 10075284B1 · Rodrigues et al. · 2018 [cited by applicant]
US 10084559B1 · Devineni · 2018 [cited by applicant]
US 10158444B1 · Darras · 2018 [cited by applicant]
US 10511312B1 · Pastorello et al. · 2019 [cited by applicant]
US 10536258B2 · Choo et al. · 2020 [cited by applicant]
US 10594423B1 · Anand et al. · 2020 [cited by applicant]
US 10715307B1 · Jin · 2020 [cited by applicant]
US 10727845B1 · Balakrishnan · 2020 [cited by applicant]
US 10797686B1 · Terstrup et al. · 2020 [cited by applicant]
US 10917097B1 · Meyer et al. · 2021 [cited by applicant]
US 10951216B1 · Barnette et al. · 2021 [cited by applicant]
US 11061432B2 · Sarda · 2021 [cited by applicant]
US 11088816B1 · Sarda · 2021 [cited by applicant]
US 11088819B1 · Sarda · 2021 [cited by applicant]
US 11502812B1 · Sarda · 2022 [cited by examiner]
US 20050232367A1 · North · 2005 [cited by examiner]
US 20060020733A1 · Sarda · 2006 [cited by applicant]
US 20060280182A1 · Williams et al. · 2006 [cited by applicant]
US 20070046516A1 · Dornbusch · 2007 [cited by applicant]
US 20080080563A1 · Kataria · 2008 [cited by applicant]
US 20080240169A1 · Cui et al. · 2008 [cited by applicant]
US 20090024865A1 · Fugaro et al. · 2009 [cited by applicant]
US 20090168808A1 · Cho · 2009 [cited by applicant]
US 20090251226A1 · Kathuria et al. · 2009 [cited by applicant]
US 20090303924A1 · Patil · 2009 [cited by examiner]
US 20100118894A1 · Aweya et al. · 2010 [cited by applicant]
US 20110296226A1 · Sorbara et al. · 2011 [cited by applicant]
US 20120300795A1 · Joergensen · 2012 [cited by applicant]
US 20120319734A1 · Nagaraj · 2012 [cited by applicant]
US 20130121347A1 · Saito et al. · 2013 [cited by applicant]
US 20140068315A1 · Aweya et al. · 2014 [cited by applicant]
US 20140320181A1 · Mitric · 2014 [cited by applicant]
US 20150092797A1 · Aweya · 2015 [cited by applicant]
US 20150185759A1 · Hinderer et al. · 2015 [cited by applicant]
US 20150200770A1 · Rahbar et al. · 2015 [cited by applicant]
US 20150207620A1 · Colby · 2015 [cited by applicant]
US 20150222276A1 · Milijevic · 2015 [cited by applicant]
US 20160170439A1 · Aweya · 2016 [cited by applicant]
US 20160182217A1 · Hashizume · 2016 [cited by applicant]
US 20170135053A1 · Shenoi et al. · 2017 [cited by applicant]
US 20170288801A1 · Aweya · 2017 [cited by applicant]
US 20170373824A1 · Mitchler · 2017 [cited by applicant]
US 20190020333A1 · Koch et al. · 2019 [cited by applicant]
US 20190036804A1 · Mihelic et al. · 2019 [cited by applicant]
US 20190379474A1 · Coulter · 2019 [cited by applicant]
US 20190379475A1 · Seethamraju · 2019 [cited by applicant]
US 20200021379A1 · Aweya · 2020 [cited by applicant]
US 20200028666A1 · Goldin et al. · 2020 [cited by applicant]
US 20200050575A1 · Mishra et al. · 2020 [cited by applicant]
US 20200127752A1 · Tai et al. · 2020 [cited by applicant]
US 20200285265A1 · Ranganathan et al. · 2020 [cited by applicant]
US 20210157355A1 · Sarda et al. · 2021 [cited by applicant]
US 20210297083A1 · Nishikawa · 2021 [cited by applicant]
US 20210328758A1 · Sarda · 2021 [cited by applicant]
CN 102291233 · 2011 [cited by applicant]
CN 103684727 · 2014 [cited by applicant]
CN 104378193 · 2015 [cited by applicant]
CN 107294634 · 2017 [cited by applicant]
WO WO2015003364 · 2015 [cited by applicant]
Broadcom Corp., “Ethernet Time Synchronization Providing Native Timing Within the Network,” White Paper, Oct. 2008, 36 pages. [cited by applicant]
NXP Semiconductors, AN-12149, Implementing an IEEE 1588 V2 on i.MX RT Using PTPd, FreeRTOS, and IwIP IrCP/IP stack, Sep. 2018 (Year 2018), 28 pages. [cited by applicant]
Eidson, J., “IEEE-1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems,” Agilent Technologies, 2005, 94 pages. [cited by applicant]
Gallant, D., “Practical Implementation of a IEEE 1588 Based Synchronization Distribution System,” Silicon Laboratories, WSTS Jun. 19, 2018, 15 pages. [cited by applicant]
International Telecommunication Union, G.8273/Y.1368 (2018)—Amendment 1, Framework of phase and time clocks, ITU-T, Mar. 2020 (Year 2020) 38 pages. [cited by applicant]
Renesas, “Synchronization Management Unit,” 8A34002 Datasheet, Renesas Electronics Corporation, Sep. 8, 2020, 107 pages. [cited by applicant]
Renesas, 82P33831, Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet, Jul. 10, 2018 (Year 2018) 75 pages. [cited by applicant]
Renesas, AN-1033, “Delay Variation Measurement and Compensation”, Application Note, Feb. 8, 2019 (Year: eo19) 13 pages. [cited by applicant]
Renesas, AN-950, “82P338XX/9XX Usage of a SYNC Input for Clock Alignment”, Application Nole, Nov. 10, eo16 (Year: 2016) 13 pages. [cited by applicant]
Silicon Labs, “UG103.05: IoT Endpoint Security Fundamentals,” silabs.com, Rev. 1.2, downloaded Oct. 22, 2020, 12 pages. [cited by applicant]
Stanton, K., 802.1AS Tutorial, Intel Corporation, Nov. 13, 2008, 42 pages. [cited by applicant]
U.S. Appl. No. 17/134,818, filed Dec. 28, 2020, entitled “FSYNC Mismatch Tracking”, by Vivek Sarda. [cited by applicant]
U.S. Appl. No. 16/836,713, filed Mar. 31, 2020, entitled “Secondary Phase Compensation Assist for PLLIO Delay Aligning Sync Signal to System Clock Signal”, by Vivek Sarda. [cited by applicant]
U.S. Appl. No. 16/836,706, filed Mar. 31, 2020, entitled “Secondary Phase Compensation Assist for PLLIO Delay”, by Vivek Sarda. [cited by applicant]
Cited By (1)
US 12,567,919