Multiple patterning scheme integration with planarized cut patterning
A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels, and applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.
1. A method for fabricating a semiconductor device integrating a multiple patterning scheme, comprising:
forming a plurality of mandrels from a base structure including a first dielectric layer formed on a cap layer, a hard mask layer formed on the first dielectric layer, and a second dielectric layer formed on the hard mask layer, the plurality of mandrels including material from the second dielectric layer;
forming a memorization layer over the plurality of mandrels and a plurality of non-mandrels; and
applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.
2. The method of claim 1 , further comprising forming the plurality of non-mandrels to include a hard mask material having an etch property substantially similar to that of the plurality of mandrels.
3. The method of claim 2 , further comprising:
forming a spacer layer;
performing an etch back of the spacer layer to form gaps between the plurality of mandrels;
forming the hard mask material in the gaps; and
performing an etch back to form the plurality of non-mandrels.
4. The method of claim 1 , wherein the hard mask material includes spin-on-glass (SOG) or spin-on-carbon (SOC).
5. The method of claim 1 , wherein applying the exposure scheme to the memorization layer further includes:
performing a first lithography exposure to create at least one mandrel cut pattern region;
performing a first etch process to remove a first portion of the memorization layer corresponding to the at least one mandrel cut pattern region;
performing a second lithography exposure to create at least one non-mandrel cut pattern region;
performing a second etch process to remove a second portion of the memorization layer corresponding to the at least one non-mandrel cut pattern region; and
forming the cut patterns within the removed portions of the memorization layer.
6. The method of claim 1 , wherein the cut patterns include silicon nitride (SiN).
7. The method of claim 1 , wherein the cap layer includes a metal cap layer.
8. The method of claim 1 , further comprising:
removing mandrels and non-mandrels not covered by the mandrel and non-mandrel cut patterns;
removing the mandrel and non-mandrel cut patterns;
removing exposed portions of the hard mask layer; and
removing exposed portions of the first dielectric layer.
9. A method for fabricating a semiconductor device integrating a multiple patterning scheme, comprising:
etching back a spacer layer to form gaps between a plurality of mandrels;
forming a plurality of non-mandrels including hard mask material having an etch property substantially similar to that of the plurality of mandrels, including:
forming the hard mask material in gaps between the plurality of mandrels; and
performing an etch back after forming the hard mask material;
forming a memorization layer over the plurality of mandrels and the plurality of non-mandrels; and
applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.
10. The method of claim 9 , further comprising forming the spacer layer.
11. The method of claim 9 , wherein the hard mask material includes spin-on-glass (SOG) or spin-on-carbon (SOC).
12. The method of claim 9 , wherein applying the exposure scheme to the memorization layer further includes:
performing a first lithography exposure to create at least one mandrel cut pattern region;
performing a first etch process to remove a first portion of the memorization layer corresponding to the at least one mandrel cut pattern region;
performing a second lithography exposure to create at least one non-mandrel cut pattern region;
performing a second etch process to remove a second portion of the memorization layer corresponding to the at least one non-mandrel cut pattern region; and
forming the cut patterns within the removed portions of the memorization layer.
13. The method of claim 9 , wherein the cut patterns include silicon nitride (SiN).
14. The method of claim 9 , further comprising forming the plurality of mandrels from a base structure, wherein the base structure includes a metal cap layer, a first dielectric layer formed on the metal cap layer, a hard mask layer formed on the first layer, and a second dielectric layer formed on the hard mask layer, and wherein the plurality of mandrels includes material from the second dielectric layer.
15. The method of claim 14 , further comprising:
removing mandrels and non-mandrels not covered by the mandrel and non-mandrel cut patterns;
removing the mandrel and non-mandrel cut patterns;
removing exposed portions of the hard mask layer; and
removing exposed portions of the first dielectric layer.
16. A method for fabricating a semiconductor device integrating a multiple patterning scheme, comprising:
forming a plurality of mandrels from a base structure including a metal cap layer, a first dielectric layer formed on the metal cap layer, a hard mask layer formed on the first dielectric layer, and a second dielectric layer formed on the hard mask layer, wherein the plurality of mandrels includes material from the second dielectric layer;
forming a plurality of non-mandrels including hard mask material having an etch property substantially similar to that of the plurality of mandrels;
forming a memorization layer over the plurality of mandrels and the plurality of non-mandrels; and
applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern, including:
performing a first lithography exposure to create at least one mandrel cut pattern region;
performing a first etch process to remove a first portion of the memorization layer corresponding to the at least one mandrel cut pattern region;
performing a second lithography exposure to create at least one non-mandrel cut pattern region;
performing a second etch process to remove a second portion of the memorization layer corresponding to the at least one non-mandrel cut pattern region; and
forming the cut patterns within the removed portions of the memorization layer.
17. The method of claim 16 , further comprising:
forming a spacer layer;
performing an etch back of the spacer layer to form gaps between the mandrels;
forming the hard mask material in the gaps; and
performing an etch back to form the plurality of non-mandrels.
18. The method of claim 16 , further comprising:
removing mandrels and non-mandrels not covered by the mandrel and non-mandrel cut patterns;
removing the mandrel and non-mandrel cut patterns;
removing exposed portions of the hard mask layer; and
removing exposed portions of the first dielectric layer.
19. The method of claim 16 , wherein the hard mask material includes spin-on-glass (SOG) or spin-on-carbon (SOC), and wherein the cut patterns include silicon nitride (SiN).