IP Library › Granted Patent US 12,293,923
Granted Patent B2
US 12,293,923 · App. 17/726,673 · Granted May 6, 2025

Method of fabricating semiconductor device

Inventor: Yangsoo Son (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/32H01L21/31053H01L21/47
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Quick Facts
Patent No.
US 12,293,923
App. No.
17/726,673
Granted
May 6, 2025
Kind
B2
Abstract

A method of fabricating a semiconductor device includes forming a cut-off region in at least one mandrel line among a plurality of mandrel lines, conformally forming a spacer material layer in the plurality of mandrel lines and a non-mandrel area and forming a cut spacer in the cut-off region and depositing a gap-fill material such that a cut block is formed on a portion of the non-mandrel area and a concave portion of the cut spacer is filled.

Claims (60)

1. A method of fabricating a semiconductor device, comprising:

forming a hard mask layer on a target layer;

forming, on the hard mask layer, a plurality of mandrel lines each having sidewalls extending in a first direction and arranged in a second direction intersecting the first direction such that the plurality of mandrel lines define a non-mandrel area;

forming a cut-off region in at least one of the plurality of mandrel lines;

forming a spacer material layer such that the spacer material layer is conformally formed on the plurality of mandrel lines and the non-mandrel area and the spacer material layer includes a cut spacer in the cut-off region;

depositing a gap-fill material such that the gap-fill material is formed on the cut spacer and the gap-fill material includes a cut block on a portion of the non-mandrel area;

etching back the spacer material layer such that sidewall spacers are formed on the sidewalls of the plurality of mandrel lines and a region, except for the cut block, of upper surfaces of the plurality of mandrel lines and the non-mandrel area is exposed;

selectively removing the plurality of mandrel lines from the sidewall spacers;

using the cut spacer, the cut block, and the sidewall spacers to form a mask pattern by etching the hard mask layer; and

etching the target layer using the mask pattern.

2. The method of claim 1 , wherein

the target layer includes a dielectric layer, and

the etching of the target layer includes forming a plurality of trenches in the dielectric layer using the mask pattern.

3. The method of claim 2 , further comprising:

filling the plurality of trenches with a conductive material such that a plurality of wiring lines is formed in the plurality of trenches.

4. The method of claim 1 , wherein a thickness of the spacer material layer is less than 50% of a width of the cut-off region in the first direction.

5. The method of claim 1 , wherein a thickness of the spacer material layer is 10 nm or less.

6. The method of claim 1 , wherein in a cross section in the first direction, the cut spacer has a concave portion.

7. The method of claim 6 , wherein the concave portion of the cut spacer extends in the second direction.

8. The method of claim 6 , wherein the depositing of the gap-fill material includes filling the concave portion of the cut spacer with the gap-fill material.

9. The method of claim 1 , wherein

the depositing of the gap-fill material includes using a mask,

the mask including a first opening exposing the cut spacer and a second opening exposing the portion of the non-mandrel area on which the cut block is to be formed.

10. The method of claim 9 , wherein the depositing of the gap-fill material includes an atomic layer deposition method.

11. The method of claim 1 , wherein the spacer material layer and the gap-fill material include different materials.

12. A method of fabricating a semiconductor device, comprising:

forming a dielectric layer on a substrate;

forming a hard mask layer on the dielectric layer;

forming a plurality of mandrel lines on the hard mask layer such that the plurality of mandrel lines define a non-mandrel area;

forming a cut-off region in at least one of the plurality of mandrel lines;

forming a spacer material layer such that the spacer material layer is conformally formed on the plurality of mandrel lines and in the non-mandrel area, and the spacer material layer includes a cut spacer having a concave portion in the cut-off region;

depositing a gap-fill material such that the gap-fill material fills the concave portion of the cut spacer and the gap-fill material includes a cut block on a portion of the non-mandrel area;

etching back the spacer material layer such that sidewall spacers are formed on sidewalls of the plurality of mandrel lines, and a region, except for the cut block, of upper surfaces of the plurality of mandrel lines and the non-mandrel area is exposed;

selectively removing the plurality of mandrel lines from the sidewall spacers;

using the cut spacer, the cut block, and the sidewall spacers to form a mask pattern by etching the hard mask layer;

forming a plurality of trenches in the dielectric layer using the mask pattern; and

filling the plurality of trenches with a conductive material such that a plurality of wiring lines is formed in the plurality of trenches.

13. The method of claim 12 , wherein

the sidewall spacers have a first interval defined by a width of the one of the plurality of mandrel lines and a second interval defined by a width of an exposed region of the non-mandrel area, and

the first interval and the second interval are equal to each other.

14. The method of claim 12 , wherein the cut block is adjacent to the cut spacer in a direction in which the plurality of mandrel lines are arranged.

15. The method of claim 12 , wherein

the spacer material layer includes titanium oxide, and

the gap-fill material includes silicon oxide.

16. The method of claim 12 , wherein the hard mask layer includes a first hard mask layer including a first material and a second hard mask layer including a second material different from the first material.

17. The method of claim 16 , wherein

the first material includes titanium nitride, and

the second material includes silicon oxide, silicon oxynitride, or silicon nitride.

18. The method of claim 12 , wherein the plurality of mandrel lines includes amorphous silicon.

19. A method of fabricating a semiconductor device, comprising:

forming a hard mask layer on a target layer;

forming, on the hard mask layer, a plurality of mandrel lines each having sidewalls extending in a first direction and arranged in a second direction intersecting the first direction such that the plurality of mandrel lines define a non-mandrel area;

forming a cut-off region in at least one of the plurality of mandrel lines;

forming a spacer material layer such that the spacer material layer is conformally formed on the plurality of mandrel lines and the non-mandrel area and the spacer material layer includes a cut spacer having a concave portion in the cut-off region;

depositing a gap-fill material such that the gap-fill material fills the concave portion of the cut spacer, and the gap-fill material includes a cut block on a portion of the non-mandrel area, the cut block positioned adjacent to the cut spacer in the second direction;

etching back the spacer material layer such that sidewall spacers are formed on the sidewalls of the plurality of mandrel lines, respectively;

selectively removing the plurality of mandrel lines from the sidewall spacers;

using the cut spacer, the cut block, and the sidewall spacers to form a mask pattern by etching the hard mask layer; and

etching the target layer using the mask pattern.

20. The method of claim 19 , wherein a gap-fill material portion of the cut block is connected to a gap-fill material portion of the cut spacer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2022
From: SON, YANGSOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059783/0284 →
Priority Claims (1)
KR 10-2021-0120349 · Sep 9, 2021 · national
Continuity (1)
Related Publication 20230075390A1 · Mar 9, 2023
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