Three-dimensional memory device containing ferroelectric memory elements encapsulated by transition metal nitride materials and method of making thereof
A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.
1. A three-dimensional ferroelectric memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein each of the electrically conductive layers comprises a respective transition metal nitride liner and a respective conductive fill material layer;
a vertical semiconductor channel vertically extending through the alternating stack;
a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers; and
discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.
2. The three-dimensional ferroelectric memory device of claim 1 , wherein:
the discrete ferroelectric material portions comprise hafnium oxide which has a predominant non-centrosymmetric orthorhombic phase and which is doped with at least one dopant selected from Al, Si, Gd, La, Y, Sr or Zr;
the transition metal nitride spacers comprise TiN or TaN spacers; and
the transition metal nitride liner comprises a TiN or TaN liner.
3. The three-dimensional ferroelectric memory device of claim 2 , further comprising a continuous dielectric material layer, wherein the continuous dielectric material layer comprises a vertical stack of the discrete ferroelectric material portions located at the levels of the electrically conductive layers and a vertical stack of non-ferroelectric dielectric material portions located at levels of the insulating layers.
4. The three-dimensional ferroelectric memory device of claim 3 , wherein the non-ferroelectric material portions comprise hafnium oxide which has a predominant monoclinic, cubic or tetragonal phase and which is doped with at least one dopant selected from Al, Si, Gd, La, Y, Sr or Zr.
5. The three-dimensional ferroelectric memory device of claim 3 , wherein an outer sidewall of the continuous dielectric material layer has a laterally-undulating profile along a vertical direction and includes laterally-protruding surfaces at each level of the electrically conductive layers.
6. The three-dimensional ferroelectric memory device of claim 1 , wherein:
the discrete ferroelectric material portions comprise vertical stacks of discrete ferroelectric material spacers; and
ferroelectric material spacers within each vertical stack of discrete ferroelectric material spacers are vertically spaced apart and have a respective vertical extent that is not greater than a vertical spacing between a vertically neighboring pair of insulating layers.
7. The three-dimensional ferroelectric memory device of claim 6 , wherein each of the discrete ferroelectric material spacers embeds a respective one of the transition metal nitride spacers and comprises:
a cylindrical ferroelectric material segment that contacts a respective one of the electrically conductive layers;
an upper annular ferroelectric material segment that contacts the respective overlying insulating layer; and
a lower annular segment that contacts the respective underlying insulating layer, wherein an inner sidewall of the upper annular segment and an inner sidewall of the lower annular segment are vertically coincident with an inner sidewall of the respective one of the transition metal nitride spacers.
8. The three-dimensional ferroelectric memory device of claim 1 , further comprising a gate dielectric layer that laterally surrounds a respective vertical semiconductor channel, and is laterally surrounded by a respective vertical stack of transition metal nitride spacers.
9. The three-dimensional ferroelectric memory device of claim 8 , wherein the gate dielectric layer comprises:
a straight outer sidewall that extends through each layer of the alternating stack and contacting the respective vertical stack of transition metal nitride spacers; and
a straight inner sidewall that extends through each layer of the alternating stack and contacting the respective vertical semiconductor channel.
10. The three-dimensional ferroelectric memory device of claim 8 , wherein:
the gate dielectric layer has a laterally undulating vertical cross-sectional profile; and
laterally protruding segments of the gate dielectric layer contact a respective one of the transition metal nitride spacers; and
connecting segments of the gate dielectric layer that connect a vertically neighboring pair of laterally protruding segments contact a respective one of the insulating layers.
11. The three-dimensional ferroelectric memory device of claim 1 , wherein:
each of the discrete ferroelectric material portions is in contact with a respective one of the transition metal nitride spacers, and with a respective one of the transition metal nitride liners; and
each of the transition metal nitride spacers contacts a sidewall of the vertical semiconductor channel.
12. The three-dimensional ferroelectric memory device of claim 1 , wherein the vertical semiconductor channel has a solid cylindrical shape.
13. The three-dimensional ferroelectric memory device of claim 1 , wherein the vertical semiconductor channel has a hollow cylindrical shape, and a dielectric core containing at least one void is surrounded by the vertical semiconductor channel.