Granted Patent B2

US 12,363,905 · App. 17/820,997 · Granted Jul 15, 2025

Inventors: Kartik Sondhi (Milpitas, CA); Rahul Sharangpani (Fremont, CA); Raghuveer S. Makala (Campbell, CA); Tiffany Santos (Palo Alto, CA); Fei Zhou (San Jose, CA); Joyeeta Nag (San Jose, CA); Bhagwati Prasad (San Jose, CA); Adarsh Rajashekhar (Santa Clara, CA)

Assignee: Sandisk Technologies, Inc.

H10B51/20H10B51/30

Abstract

Claims (51)

1. A semiconductor memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising:

a vertical semiconductor channel;

a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers and comprising a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material; and

a vertical stack of discrete dielectric material portions comprising the first dielectric metal oxide material and vertically interlaced with the vertical stack of discrete ferroelectric material portions;

wherein:

each discrete dielectric material portion has a first lateral thickness between a respective inner sidewall and a respective outer sidewall;

each of the discrete ferroelectric material portions has a second lateral thickness between a respective inner sidewall and the respective outer sidewall; and

the second lateral thickness is greater than the first lateral thickness.

2. The semiconductor memory device of claim 1 , wherein the inner sidewalls of the discrete dielectric material portions and the inner sidewalls of the discrete ferroelectric material portions are vertically coincident.

3. The semiconductor memory device of claim 1 , wherein:

each inner sidewall of the discrete ferroelectric material portions comprises a respective first inner cylindrical sidewall;

each outer sidewall of the discrete ferroelectric material portions comprises a respective first outer cylindrical sidewall;

each inner sidewall of the discrete dielectric material portions comprises a respective second inner cylindrical sidewall; and

each outer sidewall of the discrete dielectric material portions comprises a respective second outer cylindrical sidewall.

4. A semiconductor memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising:

a vertical semiconductor channel;

a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers and comprising a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material; and

a vertical stack of discrete dielectric material portions comprising the first dielectric metal oxide material and vertically interlaced with the vertical stack of discrete ferroelectric material portions;

wherein each of the discrete ferroelectric material portions comprises a respective outer sidewall that laterally protrudes outward by a greater lateral distance from a vertical axis passing through a geometrical center of the memory opening fill structure than interfaces between the memory opening fill structure and the insulating layers laterally protrude from the vertical axis.

5. A semiconductor memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising:

a vertical semiconductor channel;

a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers and comprising a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material; and

vertical stack of discrete dielectric material portions comprising the first dielectric metal oxide material and vertically interlaced with the vertical stack of discrete ferroelectric material portions; and

further comprising second dielectric metal oxide layers comprising the second dielectric metal oxide material are interposed between vertically neighboring pairs of an insulating layer of the insulating layers and an electrically conductive layer of the electrically conductive layers.

6. The semiconductor memory device of claim 5 , wherein each of the second dielectric metal oxide layers is in direct contact with an outer sidewall of a respective one of the discrete ferroelectric material portions.

7. The semiconductor memory device of claim 6 , wherein one of the second dielectric metal oxide layers comprises:

a first horizontally-extending portion contacting a bottom surface of an overlying insulating layer of the insulating layers;

a second horizontally-extending portion contacting a top surface of an underlying insulating layer of the insulating layers; and

a tubular portion connecting the first horizontally-extending portion and the second horizontally-extending portion and laterally surrounding the memory opening fill structure.

8. The semiconductor memory device of claim 7 , wherein:

the cylindrical portion has a uniform lateral thickness between an inner sidewall and an outer sidewall;

the first horizontally-extending portion and the second horizontally-extending portion have a uniform vertical thickness; and

the uniform lateral thickness is less than the uniform vertical thickness.

9. The semiconductor device of claim 5 , wherein the electrically conductive layers are in direct contact with an outer sidewall of a respective one of the discrete ferroelectric material portions, and an entirety of the outer sidewall of each of the discrete ferroelectric material portions is in direct contact with a cylindrical sidewall of a respective one of the electrically conductive layers.

10. A semiconductor memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising:

a vertical semiconductor channel;

a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers and comprising a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material; and

vertical stack of discrete dielectric material portions comprising the first dielectric metal oxide material and vertically interlaced with the vertical stack of discrete ferroelectric material portions;

wherein the vertical stack of discrete ferroelectric material portions is in direct contact with cylindrical surface segments of the vertical semiconductor channel.

Assignments (4)

Continuity (1)

References Cited (42)