Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel;
wherein the vertical semiconductor channel of each of the memory stack structures directly contacts each single crystalline ferroelectric dielectric layer in the same memory stack structure.
2. The three-dimensional memory device of claim 1 , wherein each single crystalline ferroelectric dielectric layer within the vertical stack is epitaxially aligned to the vertical semiconductor channel within each of the memory stack structures.
3. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel;
wherein:
each vertically neighboring pair of an insulating layer and an electrically conductive layer is vertically spaced from each other by a respective polycrystalline ferroelectric material layer; and
the polycrystalline ferroelectric material layer has a same material composition and a same thickness as the single crystalline ferroelectric dielectric layers in the vertical stacks of single crystalline ferroelectric dielectric layers.
4. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming openings through the alternating stack;
forming vertical semiconductor channels comprising a respective single crystalline semiconductor material in the openings through the alternating stack;
forming backside recesses by removing the sacrificial material layers;
forming vertical stacks of single crystalline ferroelectric dielectric layers, wherein each vertical stack of single crystalline ferroelectric dielectric layers is formed adjacent to a respective one of the vertical semiconductor channels; and
forming electrically conductive layers on the vertical stacks of single crystalline ferroelectric dielectric layers in remaining volumes of the backside recesses;
wherein each of the single crystalline ferroelectric dielectric layers is formed in epitaxial alignment with, and in direct contact with, a respective one of the vertical semiconductor channels.
5. The method of claim 4 , further comprising:
conformally depositing an amorphous ferroelectric dielectric material layer in the backside recesses and directly on physically exposed outer sidewalls of the vertical semiconductor channels; and
inducing a templated crystalline growth of the amorphous ferroelectric dielectric material layer employing the vertical semiconductor channels as an epitaxial template by performing an anneal process, wherein portions of the amorphous ferroelectric dielectric material layer that are proximal to the vertical semiconductor channels are transformed into the single crystalline ferroelectric dielectric layers and portions of the amorphous ferroelectric dielectric material layer that are not proximal to the vertical semiconductor channels are transformed into polycrystalline ferroelectric dielectric layers or remain amorphous.
6. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming openings through the alternating stack;
forming vertical semiconductor channels comprising a respective single crystalline semiconductor material in the openings through the alternating stack;
forming backside recesses by removing the sacrificial material layers;
forming vertical stacks of single crystalline ferroelectric dielectric layers, wherein each vertical stack of single crystalline ferroelectric dielectric layers is formed adjacent to a respective one of the vertical semiconductor channels;
forming electrically conductive layers on the vertical stacks of single crystalline ferroelectric dielectric layers in remaining volumes of the backside recesses;
forming an array of line trenches through the alternating stack, wherein the line trenches laterally extend along a first horizontal direction and are laterally spaced apart along a second horizontal direction;
filling each of the line trenches with a respective set of dielectric material portions that define rows of vertical cavities, wherein each of the vertical semiconductor channels is formed within a respective one of the vertical cavities;
forming a combination of a pair of sacrificial material rails and a dielectric material rail in each of the line trenches;
dividing each combination of the pair of sacrificial material rails and the dielectric material rail into multiple composite pillar structures including a respective dielectric core and a respective pair of sacrificial material strips, wherein pillar cavities are formed in volumes from which portions of the sacrificial material rails and the dielectric material rails are removed;
forming dielectric pillar structures in the pillar cavities; and
forming the vertical cavities by removing the sacrificial material strips selective to the dielectric pillar structures and the dielectric cores.