Three-dimensional flat NAND memory device having high mobility channels and methods of making the same
A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
1. A method of forming a three-dimensional memory device, comprising:
forming alternating stacks of insulating strips and spacer material strips located over a substrate, wherein the alternating stacks are laterally spaced apart among one another by line trenches laterally extending along a first horizontal direction, and wherein the spacer material strips are formed as, or are subsequently replaced with, electrically conductive strips;
forming line trench fill structures within the line trenches, wherein each line trench fill structure fills a respective one of the line trenches, and each line trench fill structure comprises a pair of memory film layers and a seed semiconductor material layer;
forming a two-dimensional array of pillar cavities through the line trench fill structures, wherein an alternating two-dimensional array of pillar structures and pillar cavities are formed, and each pillar structure comprises a remaining portion of the line trench fill structures; and
selectively growing replacement semiconductor channel layers from remaining portions of the seed semiconductor material layers to form vertical semiconductor channels.
2. The method of claim 1 , further comprising partially recessing the seed semiconductor material layers to form lateral recesses adjacent to the pillar cavities after formation of the pillar cavities, wherein the replacement semiconductor channel layers are formed within the lateral recesses.
3. The method of claim 2 , wherein physically exposed surfaces of remaining portions of the seed semiconductor material layers at a step of selective growth of the replacement semiconductor channel layer is substantially perpendicular to the first horizontal direction, and growth of the replacement semiconductor channel layers occurs along the first horizontal direction and with a larger average grain size than an average grain size of the remaining portions of the seed semiconductor material layers.
4. The method of claim 3 , further comprising forming dielectric pillar structures by depositing a dielectric material within volumes of the pillar cavities, wherein each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures, and wherein each of the memory stack assemblies comprises a respective one of the vertical semiconductor channels.
5. The method of claim 1 , wherein:
the seed semiconductor material layer comprises germanium or silicon germanium;
the replacement semiconductor channel layers comprise silicon channels which are formed within volumes of the pillar cavities; and
the method further comprises removing all remaining portions of the seed semiconductor material layers.
6. The method of claim 5 , further comprising forming dielectric pillar structures by depositing a dielectric material within volumes from which the seed semiconductor material layers are removed.
7. A method of forming a three-dimensional memory device, comprising:
forming alternating stacks of insulating strips and spacer material strips located over a semiconductor substrate, wherein the alternating stacks are laterally spaced apart among one another by line trenches laterally extending along a first horizontal direction, and wherein the spacer material strips are formed as, or are subsequently replaced with, electrically conductive strips;
forming line trench fill structures within the line trenches, wherein each line trench fill structure fills a respective one of the line trenches, and each line trench fill structure comprises a pair of memory film layers and a sacrificial semiconductor material layer;
forming a two-dimensional array of dielectric pillar structures through the line trench fill structures to form an alternating two-dimensional array of the dielectric pillar structures and remaining portions of the line trench fill structures;
forming channel cavities by removing the sacrificial semiconductor material layers; and
forming vertical semiconductor channels in the channel cavities by selectively growing replacement semiconductor channel layers from physically exposed surfaces of the semiconductor substrate.
8. The method of claim 7 , wherein each channel cavity is a U-shaped cavity including a horizontal bottom portion and a pair of vertically-extending portions adjoining the horizontal bottom portion.
9. The method of claim 7 , further comprising:
forming a two-dimensional array of pillar cavities through the line trench fill structures; and
depositing a dielectric material in the two-dimensional array of pillar cavities to form the two-dimensional array of dielectric pillar structures.