Semiconductor structure and a method of making thereof
An integrated circuit package comprising a first substrate having a cavity; a second substrate; and one or more semiconductor device(s) and/or passive component (s) are coupled to the second substrate. The cavity is formed using two opposite side walls of the first substrate where two opposite sides of the cavity are kept open, the one or more semiconductor device(s) and/or passive component(s) is/are electrically coupled using redistribution layers, and the second substrate is located inside the cavity of the first substrate.
1. An integrated circuit package comprising:
a first substrate having a cavity/clearance, wherein
said cavity/clearance is formed using two opposite side walls of the first substrate, and
said two opposite sides of the cavity/clearance are open;
a second substrate; and
one or more component(s) is/are coupled to the second substrate, wherein
said second substrate is located inside the cavity/clearance of the first substrate,
said second substrate is a passive substrate and not an active chip, and
said cavity/clearance is formed using two standoff substrates coupled to the first substrate while the two opposite sides of the cavity/clearance are open.
2. The integrated circuit package according to claim 1 , wherein
said first substrate and said second substrate are electrically coupled using wire and/or redistribution layer.
3. The integrated circuit package according to claim 1 , wherein
said cavity/clearance is formed along the periphery of the first substrate.
4. The integrated circuit package according to claim 1 , wherein
at least one of said one or more component(s) is/are electrically coupled to the first substrate and/or second substrate.
5. The integrated circuit package according to claim 1 , wherein
at least one of said one or more component(s) is/are electrically coupled to the first substrate using a flip chip or a wirebond method.
6. The integrated circuit package according to claim 1 , wherein
said cavity/clearance contains active and/or passive component(s).
7. The integrated circuit package according to claim 1 , wherein
said first substrate and/or said second substrate contains one or more through holes and/or cavities.
8. The integrated circuit package according to claim 1 , wherein
at least one substrate of said first substrate and/or second substrate comprises of RDL and/or through substrate via.
9. The integrated circuit package according to claim 1 , wherein
one of said one or more component(s) is/are an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-fill or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.
10. The integrated circuit package according to claim 1 , wherein
at least one substrate of said first substrate and/or second substrate and at least one component of said one or more component(s) is/are manufactured as one piece.
11. A system comprising:
a first substrate having a cavity/clearance; wherein
said cavity/clearance is formed using two opposite side walls of the first substrate, and
two opposite sides of the cavity/clearance are open; and
a second substrate, wherein
said second substrate is located inside the cavity/clearance of the first substrate,
said second substrate is a passive substrate and not an active chip, and
said cavity/clearance is formed using two standoff substrates coupled to the first substrate while the two opposite sides of the cavity/clearance are open.
12. A system comprising:
a first substrate having a cavity/clearance, wherein
said cavity/clearance is formed using one wall of the first substrate, and
opposite sides of the cavity/clearance are open; and
a second substrate, wherein
said second substrate is located inside the cavity/clearance of the first substrate,
said second substrate is a passive substrate and not an active chip, and
said cavity/clearance is formed using two standoff substrates coupled to the first substrate while the two opposite sides of the cavity/clearance are open.
13. An integrated circuit package comprising:
a first substrate having a cavity/clearance, wherein
said cavity/clearance is formed using two opposite side walls of the first substrate, and
said two opposite sides of the cavity/clearance are open;
a second substrate; and
one or more component(s) is/are coupled to the second substrate, wherein
said second substrate is located inside the cavity/clearance of the first substrate,
said second substrate is a passive substrate and not an active chip, and
said cavity/clearance is formed using two standoff substrates coupled to the first substrate while the two adjacent sides of the cavity/clearance are open.
14. A system comprising
a first substrate having a cavity/clearance; wherein
said cavity/clearance is formed using two opposite side walls of the first substrate, and
two opposite sides of the cavity/clearance are open; and
a second substrate, wherein
said second substrate is located inside the cavity/clearance of the first substrate,
said second substrate is a passive substrate and not an active chip, and
said cavity/clearance is formed using two standoff substrates coupled to the first substrate while the two adjacent sides of the cavity/clearance are open.
15. A system comprising:
a first substrate having a cavity/clearance, wherein
said cavity/clearance is formed using one wall of the first substrate, and
opposite sides of the cavity/clearance are open; and
a second substrate, wherein
said second substrate is located inside the cavity/clearance of the first substrate,
said second substrate is a passive substrate and not an active chip, and
said cavity/clearance is formed using two standoff substrates coupled to the first substrate while the two adjacent sides of the cavity/clearance are open.
16. The integrated circuit package according to claim 11 , wherein
the at least one standoff substrate comprises of two or more substrates.
17. The integrated circuit package according to claim 11 , wherein
at least one active or passive component is coupled to at least one of the said first substrate and/or second substrate and/or standoff substrate.
18. The integrated circuit package according to claim 11 , wherein
said cavity/clearance contains active and/or passive component(s).
19. The integrated circuit package according to claim 11 , wherein
said first substrate and/or said second substrate contains one or more through holes and/or cavities.
20. The integrated circuit package according to claim 11 , wherein
at least one of said first substrate and/or second substrate and/or standoff substrate comprises of RDL and/or through substrate via.
21. The integrated circuit package according to claim 17 , wherein
one of the component(s) is/are an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-fill or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.
22. The integrated circuit package according to claim 12 , wherein
the at least one standoff substrate comprises of two or more substrates.
23. The integrated circuit package according to claim 12 , wherein
at least one active or passive component is coupled to at least one of the said first substrate and/or second substrate and/or standoff substrate.
24. The integrated circuit package according to claim 12 , wherein
said cavity/clearance contains active and/or passive component(s).
25. The integrated circuit package according to claim 12 , wherein
said first substrate and/or said second substrate contains one or more through holes and/or cavities.
26. The integrated circuit package according to claim 12 , wherein
at least one of said first substrate and/or second substrate and/or standoff substrate comprises of RDL and/or through substrate via.
27. The integrated circuit package according to claim 23 , wherein
one of the component(s) is/are an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-fill or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.
28. The integrated circuit package according to claim 13 , wherein
the at least one standoff substrate comprises of two or more substrates.
29. The integrated circuit package according to claim 13 , wherein
at least one active or passive component is coupled to at least one of the said first substrate and/or second substrate and/or standoff substrate.
30. The integrated circuit package according to claim 13 , wherein
said cavity/clearance contains active and/or passive component(s).
31. The integrated circuit package according to claim 13 , wherein
said first substrate and/or said second substrate contains one or more through holes and/or cavities.
32. The integrated circuit package according to claim 13 , wherein
at least one of said first substrate and/or second substrate and/or standoff substrate comprises of RDL and/or through substrate via.
33. The integrated circuit package according to claim 29 , wherein
one of the component(s) is/are an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-fill or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.
34. The integrated circuit package according to claim 14 , wherein
the at least one standoff substrate comprises of two or more substrates.
35. The integrated circuit package according to claim 14 , wherein
at least one active or passive component is coupled to at least one of the said first substrate and/or second substrate and/or standoff substrate.
36. The integrated circuit package according to claim 14 , wherein
said cavity/clearance contains active and/or passive component(s).
37. The integrated circuit package according to claim 14 , wherein
said first substrate and/or said second substrate contains one or more through holes and/or cavities.
38. The integrated circuit package according to claim 14 , wherein
at least one of said first substrate and/or second substrate and/or standoff substrate comprises of RDL and/or through substrate via.
39. The integrated circuit package according to claim 35 , wherein
one of the component(s) is/are an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-fill or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.
40. The integrated circuit package according to claim 15 , wherein
the at least one standoff substrate comprises of two or more substrates.
41. The integrated circuit package according to claim 15 , wherein
at least one active or passive component is coupled to at least one of the said first substrate and/or second substrate and/or standoff substrate.
42. The integrated circuit package according to claim 15 , wherein
said cavity/clearance contains active and/or passive component(s).
43. The integrated circuit package according to claim 15 , wherein
said first substrate and/or said second substrate contains one or more through holes and/or cavities.
44. The integrated circuit package according to claim 15 , wherein
at least one of said first substrate and/or second substrate and/or standoff substrate comprises of RDL and/or through substrate via.
45. The integrated circuit package according to claim 41 , wherein
one of the component(s) is/are an antenna or amplifier or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or ASIC or TSV or laser or FPGA or analog circuit or digital circuit or SerDes or filter or Lens or GPU or magnet or waveguide or wirebond or mold or under-fill or heat-pipe or mirror or fan or bump or fiber or accelerator or MEMS or membrane or heat spreader or RDL or energy source or light source or battery.
46. The integrated circuit package according to claim 11 , wherein
said first substrate and said second substrate are electrically coupled using wire and/or redistribution layer.
47. The integrated circuit package according to claim 12 , wherein
said first substrate and said second substrate are electrically coupled using wire and/or redistribution layer.
48. The integrated circuit package according to claim 13 , wherein
said first substrate and said second substrate are electrically coupled using wire and/or redistribution layer.
49. The integrated circuit package according to claim 14 , wherein
said first substrate and said second substrate are electrically coupled using wire and/or redistribution layer.
50. The integrated circuit package according to claim 15 , wherein
said first substrate and said second substrate are electrically coupled using wire and/or redistribution layer.