Method of maintaining the state of semiconductor memory having electrically floating body transistor
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
1. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
a first bipolar device having a first floating base region, a first collector, and a first emitter; and
a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector;
wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors;
wherein said first and second collectors are commonly connected to at least two of said memory cells;
a buried well terminal connected to a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors; and
a control circuit configured to apply said back-bias to said buried well terminal.
2. The integrated circuit of claim 1 , wherein said first and second floating base regions have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
wherein said first and second emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
wherein said conductivity type of said first and second collectors and said region is said second conductivity type.
3. The integrated circuit of claim 1 , wherein said back-bias applied to said first and second collectors is a constant voltage bias.
4. The integrated circuit of claim 1 , wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.
5. The integrated circuit of claim 1 , wherein said at least two of said semiconductor memory cells each further comprises a gate region above said first and second floating base regions.
6. The integrated circuit of claim 1 , wherein a maximum potential that can be stored in said first and second floating base regions is increased by said applying back bias to said first and second collectors, resulting in a relatively larger memory window.
7. The integrated circuit of claim 1 , wherein said semiconductor memory cells comprise fin structures extending from a substrate.
8. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said semiconductor memory cells includes:
a first bipolar device having a first floating base region, a first collector, and a first emitter; and
a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector;
wherein application of back-bias to said first and second collectors results in at least two stable floating base region charge levels;
wherein said first and second collectors are commonly connected to at least two of said memory cells;
a buried well terminal connected to a region extending from and electrically connected to said first and second collectors, wherein said region has a conductivity type selected from a p-type conductivity type and an n-type conductivity type that is the same as a conductivity type of said first and second collectors; and
a control circuit configured to apply said back-bias to said buried well terminal.
9. The integrated circuit of claim 8 , wherein said first and second floating base regions have a first conductivity type selected from said p-type conductivity type and said n-type conductivity type;
wherein said first and second emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
said conductivity type of said first and second collectors and said region is said second conductivity type.
10. The integrated circuit of claim 8 , wherein said back-bias applied to said first and second collectors is a constant voltage bias.
11. The integrated circuit of claim 8 , wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.
12. The integrated circuit of claim 8 , wherein each said semiconductor memory cell further comprises a gate region above said first and second floating base regions.
13. The integrated circuit of claim 8 , wherein a maximum potential that can be stored in said first and second floating base regions is increased by said applying back-bias to said first and second collectors, resulting in a relatively larger memory window.
14. The integrated circuit of claim 8 , wherein said plurality of semiconductor memory cells comprise fin structures extending from a substrate.
15. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said plurality of semiconductor memory cells includes:
a first bipolar device having a first floating base region, a first collector, and a first emitter; and
a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector;
wherein states of said memory cells are maintained upon repeated read operations;
a buried well terminal connected to a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors; and
a control circuit configured to apply a back-bias to said buried well terminal.
16. The integrated circuit of claim 15 , wherein at least one of said first bipolar device or said second bipolar device maintains the state of said memory cell; and
wherein said first and second collectors are commonly connected to at least two of said memory cells.
17. The integrated circuit of claim 15 , wherein said first floating base region and said second floating base region have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;
wherein said first and second emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and
wherein said conductivity type of said first and second collectors and said region is said second conductivity type.
18. The integrated circuit of claim 15 , wherein said back-bias is applied to said first and second collectors via a voltage bias applied as a constant voltage bias, a periodic pulse of voltage, or a serial combination of constant voltage bias and periodic pulse of voltage.
19. The integrated circuit of claim 15 , wherein a maximum potential that can be stored in said first and second floating base regions is increased by applying said back-bias to the cell, resulting in a relatively larger memory window.
20. The integrated circuit of claim 15 , comprising a fin structure extending from a substrate.