IP Library Granted Patent US 11,043,590
Granted Patent B2
US 11,043,590 · App. 16/899,157 · Granted Jun 22, 2021

Semiconductor component and manufacturing method thereof

Inventor: Koichi Amari (Kanagawa, JP)
Assignee: Sony Corporation
H01L29/7834H01L29/1037H01L29/4236H01L29/66545H01L29/66583H01L29/66621H01L29/66666H01L29/7827H01L29/7843
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Quick Facts
Patent No.
US 11,043,590
App. No.
16/899,157
Granted
Jun 22, 2021
Kind
B2
Abstract

A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Claims (10)

1. A semiconductor device comprising:

a substrate; and

a transistor including a gate insulating film, a gate electrode, a first source-drain region and a second source-drain region,

wherein in a first cross section along a first direction, the gate electrode is formed above the gate insulating film along a patterned surface of the substrate, the patterned surface including periodic raised portions and recessed portions,

wherein in a second cross section along a second direction perpendicular to the first direction, at a location of one of the raised portions, a first portion of a channel between the first source-drain region and the second source-drain region has a first length,

in a third cross section along the second direction, at a location of one of the recessed portions, the recessed portion extends into the substrate between the first source-drain region and the second source-drain region, such that a second portion of the channel has a second length that is longer than the first length.

2. The semiconductor device according to claim 1 , wherein in the first cross section, the one of the recessed portions is formed in a groove that extends into the substrate, the groove having a pair of sidewalls extending between the one of the recessed portions and adjacent ones of the raised portions.

3. The semiconductor device according to claim 2 , wherein the sidewalls extend in a depth direction of the substrate.

4. The semiconductor device according to claim 2 , wherein the sidewalls are slanted with respect to a depth direction of the substrate.

5. The semiconductor device according to claim 1 , further comprising a planarizing film formed above the first and second source-drain regions and having an upper surface at a same level as an upper surface of the gate electrode.

Priority Claims (1)
JP 2009-298319 · Dec 28, 2009 · national
Continuity (6)
Continuation 15956254 · Apr 18, 2018
Continuation 15658950 · Jul 25, 2017
Continuation 15371826 · Dec 7, 2016
Continuation 14573771 · Dec 17, 2014
Continuation 12967857 · Dec 14, 2010
Related Publication 20200303546A1 · Sep 24, 2020