3D semiconductor device and structure with oxide bonds
A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal channel, where at least one of the plurality of transistors includes a second single crystal channel, where the second single crystal channel is disposed above the first single crystal channel, where at least one of the plurality of transistors includes a third single crystal channel, where the third single crystal channel is disposed above the second single crystal channel, where at least one of the plurality of transistors includes a fourth single crystal channel, and where the fourth single crystal channel is disposed above the third single crystal channel; and at least one region of oxide to oxide bonds.
1. A semiconductor device, the device comprising:
a plurality of transistors,
wherein at least one of said plurality of transistors comprises a first single crystal channel,
wherein at least one of said plurality of transistors comprises a second single crystal channel,
wherein said second single crystal channel is disposed above said first single crystal channel,
wherein at least one of said plurality of transistors comprises a third single crystal channel,
wherein said third single crystal channel is disposed above said second single crystal channel,
wherein at least one of said plurality of transistors comprises a fourth single crystal channel, and
wherein said fourth single crystal channel is disposed above said third single crystal channel; and
at least one region of oxide to oxide bonds.
2. The device according to claim 1 ,
wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.
3. The device according to claim 1 ,
wherein said at least one region of oxide to oxide bonds is underneath said third single crystal channel and above said second single crystal channel.
4. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises two side gates.
5. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises a gate all around structure.
6. The device according to claim 1 , further comprising:
a first gate structure, and
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said second single crystal channels.
7. The device according to claim 1 , further comprising:
a first gate structure, and
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said third single crystal channels.
8. A semiconductor device, the device comprising:
a plurality of transistors,
wherein at least one of said plurality of transistors comprises a first single crystal channel,
wherein at least one of said plurality of transistors comprises a second single crystal channel,
wherein said second single crystal channel is disposed above said first single crystal channel,
wherein at least one of said plurality of transistors comprises a third single crystal channel,
wherein said third single crystal channel is disposed above said second single crystal channel,
wherein at least one of said plurality of transistors comprises a fourth single crystal channel,
wherein said fourth single crystal channel is disposed above said third single crystal channel; and
at least one region of oxide to oxide bonds,
wherein said at least one region of oxide to oxide bonds is disposed underneath said third single crystal channel and above said second single crystal channel.
9. The device according to claim 8 ,
wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.
10. The device according to claim 8 , further comprising:
a single crystal substrate.
11. The device according to claim 8 ,
wherein at least one of said plurality of transistors comprises two side gates.
12. The device according to claim 8 ,
wherein at least one of said plurality of transistors comprises a gate all around structure.
13. The device according to claim 8 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said second single crystal channels.
14. The device according to claim 8 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said third single crystal channels.
15. A semiconductor device, the device comprising:
a plurality of transistors,
wherein at least one of said plurality of transistors comprises a first single crystal channel,
wherein at least one of said plurality of transistors comprises a second single crystal channel,
wherein said second single crystal channel is disposed above said first single crystal channel,
wherein at least one of said plurality of transistors comprises a third single crystal channel,
wherein said third single crystal channel is disposed above said second single crystal channel,
wherein at least one of said plurality of transistors comprises a fourth single crystal channel,
wherein said fourth single crystal channel is disposed above said third single crystal channel; and
a layer of oxide to oxide bonds; and
a single crystal substrate.
16. The device according to claim 1 ,
wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.
17. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises two side gates.
18. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises a gate all around structure.
19. The device according to claim 1 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said second single crystal channels.
20. The device according to claim 1 , further comprising:
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said third single crystal channels.