Multilevel semiconductor device and structure with image sensors
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.
1. An integrated device, the device comprising:
a first level comprising a first mono-crystal layer, said first mono-crystal layer comprising a plurality of single crystal transistors;
an overlaying oxide on top of said first level;
a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
wherein said second mono-crystal layer comprises a plurality of first image sensors; and
a third level overlaying said second level,
wherein said third level comprises a plurality of second image sensors,
wherein said second level is bonded to said first level,
wherein said bonded comprises an oxide to oxide bond; and
an isolation layer disposed between said second mono-crystal layer and said third level.
2. The integrated device according to claim 1 ,
wherein said second mono-crystal layer is less than 5 microns thick.
3. The integrated device according to claim 1 ,
wherein said first level comprises a plurality of landing pads.
4. The integrated device according to claim 1 ,
wherein said second mono-crystal layer comprises alignment marks, and
wherein said third level is aligned to said alignment marks.
5. The integrated device according to claim 1 , further comprising:
memory circuits.
6. The integrated device according to claim 1 ,
wherein said plurality of first image sensors is sensitive to a first set of light wavelengths and said plurality of second image sensors is sensitive to a second set of light wavelengths, and
wherein said first set of light wavelengths is different than said second set of light wavelengths.
7. The integrated device according to claim 1 ,
wherein said second level comprises an array of image sensor pixels,
wherein said first level comprises a plurality of pixel control circuits, and
wherein each of said image sensors pixels is directly connected to said pixel control circuits.
8. An integrated device, the device comprising:
a first level comprising a first mono-crystal layer, said first level comprising a plurality of single crystal transistors;
an overlaying oxide on top of said first level;
a second level comprising a second mono-crystal layer, said second level overlaying said oxide,
wherein said second mono-crystal layer comprises a plurality of first image sensors; and
a third level overlaying said second level,
wherein said third level comprises a plurality of second image sensors, and
wherein said second level is bonded to said first level; and
memory circuits.
9. An integrated device, the device comprising:
a first level comprising a first mono-crystal layer,
wherein said first mono-crystal layer comprises a plurality of single crystal transistors;
an overlying oxide on top of said first level;
a second level comprising a second mono-crystal layer, said second level overlaying said oxide;
a third level overlaying said second level,
wherein said third level comprises a third mono-crystal layer comprising a plurality of image sensors,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds; and
an isolation layer disposed between said second mono-crystal layer and said third level.
10. The integrated device according to claim 9 ,
wherein said second mono-crystal layer is less than 5 microns thick.
11. The integrated device according to claim 9 ,
wherein said first level comprises a plurality of landing pads.
12. The integrated device according to claim 9 , further comprising:
memory circuits.
13. The integrated device according to claim 9 ,
wherein said second mono-crystal layer comprises a plurality of second image sensors.
14. The integrated device according to claim 9 ,
wherein said third level comprises an array of image sensor pixels, and
wherein said first level comprises a plurality of pixel control circuits.