IP Library › Granted Patent US 11,443,407
Granted Patent B2
US 11,443,407 · App. 17/465,821 · Granted Sep 13, 2022

Sparse matrix optimization mechanism

Inventors: Namita Sharma (New Delhi, IN); Supratim Pal (Bangalore, IN); Biju P. Simon (Bangalore, IN); Tovinakere D. Vivek (Bangalore, IN)
Assignee: Intel Corporation
G06T1/20G06T2200/28
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Quick Facts
Patent No.
US 11,443,407
App. No.
17/465,821
Granted
Sep 13, 2022
Kind
B2
Abstract

An apparatus to facilitate matrix processing is disclosed. The apparatus comprises a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, examine a first block of the sub-blocks to determine whether the first block comprises sparse data, select a first tile size upon a determination that the first block comprises sparse data and generate output matrix data based on the first tile size.

Claims (33)

1. An apparatus comprising:

a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, retrieve bitmap data having a plurality sub-block bits, each associated with one of the plurality of sub-blocks, examine sub-block bits associated with adjacent sub-blocks in a first block to determine a tile size that is to be processed, select a first tile size for processing of the sub-blocks upon a determination that each of the sub-block bits within the bitmap data comprise a first bit value and process the sub-blocks to generate output matrix data.

2. The apparatus of claim 1 , wherein the first bit value indicates that a sub-block comprises sparse data.

3. The apparatus of claim 2 , wherein the first tile size comprises a size of the first block.

4. The apparatus of claim 3 , wherein the matrix accelerator selects a second tile size for processing of the sub-blocks upon a determination that at least one of the sub-block bits comprise a second bit value.

5. The apparatus of claim 4 , wherein the second bit value indicates that a sub-block does not comprise sparse data.

6. The apparatus of claim 5 , wherein the second tile size comprises a size of a sub-block.

7. The apparatus of claim 6 , further comprising a systolic pipeline that comprises a first configuration to process each sub-block.

8. The apparatus of claim 7 , wherein the systolic pipeline is transformed to a second configuration to process the first block of sub-blocks upon a determination that each of the sub-block bits comprise the first bit value.

9. A method comprising:

receiving input matrix data;

transforming the input matrix data into a plurality of sub-blocks;

retrieving bitmap data having a plurality sub-block bits, each associated with one of the plurality of sub-blocks;

examining sub-block bits associated with adjacent sub-blocks in a first block to determine a tile size that is to be processed block comprises sparse data;

selecting a first tile size for processing of the sub-blocks upon a determination that each of the sub-block bits within the bitmap data comprise a first bit value; and

processing the sub-blocks to generate output matrix data.

10. The method of claim 9 , wherein the first bit value indicates that a sub-block comprises sparse data.

11. The method of claim 10 , wherein the first tile size comprises a size of the first block.

12. The method of claim 11 , further comprising selecting a second tile size for processing of the sub-blocks upon a determination that at least one of the sub-block bits comprise a second bit value.

13. The method of claim 12 , wherein the second bit value indicates that a sub-block does not comprise sparse data.

14. The method of claim 13 , wherein the second tile size comprises a size of a sub-block.

15. At least one non-transitory computer readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to:

receive input matrix data;

transform the input matrix data into a plurality of sub-blocks;

retrieve bitmap data having a plurality sub-block bits, each associated with one of the plurality of sub-blocks;

examine sub-block bits associated with adjacent sub-blocks in a first block to determine a tile size that is to be processed block comprises sparse data;

select a first tile size for processing of the sub-blocks upon a determination that each of the sub-block bits within the bitmap data comprise a first bit value; and

process the sub-blocks to generate output matrix data.

16. The computer readable medium of claim 15 , wherein the first bit value indicates that a sub-block comprises sparse data.

17. The computer readable medium of claim 16 , wherein the first tile size comprises a size of the first block.

18. The computer readable medium of claim 17 , having instructions stored thereon, which when executed by one or more processors, further cause the processors to select a second tile size for processing of the sub-blocks upon a determination that at least one of the sub-block bits comprise a second bit value.

19. The computer readable medium of claim 18 , wherein the second bit value indicates that a sub-block does not comprise sparse data.

20. The computer readable medium of claim 19 , wherein the second tile size comprises a size of a sub-block.

Continuity (2)
Continuation 16710081 · Dec 11, 2019
Related Publication 20220092723A1 · Mar 24, 2022
Cited By (5)
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