Semiconductor arrangement with fin features having different heights
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
1. A semiconductor arrangement, comprising:
a first fin protruding from a substrate;
a second fin protruding from the substrate;
a first gate overlying the first fin;
a second gate overlying the second fin, wherein:
in a space between the first gate and the second gate:
a first semiconductor fin nub protrudes from the substrate, and
the substrate defines a trench disposed between the first semiconductor fin nub and the first fin; and
a dielectric layer overlying the first semiconductor fin nub and underlying the first gate.
2. The semiconductor arrangement of claim 1 , comprising:
an alignment mark overlying the substrate, wherein the dielectric layer is between the first fin and the alignment mark and overlies a first portion of the alignment mark.
3. The semiconductor arrangement of claim 2 , wherein an uppermost surface of a second portion of the alignment mark between the first portion of the alignment mark and the first fin is above the dielectric layer.
4. The semiconductor arrangement of claim 1 , wherein:
the dielectric layer has a first depth at a location vertically aligned with the trench,
the dielectric layer has a second depth at a location vertically aligned with the first semiconductor fin nub,
the dielectric layer has a third depth at a location between the trench and the first fin,
the first depth is different than the second depth and the third depth, and
the second depth is different than the third depth.
5. The semiconductor arrangement of claim 4 , wherein:
the first depth is greater than the second depth and the third depth, and
the second depth is greater than the third depth.
6. The semiconductor arrangement of claim 1 , comprising:
a first semiconductor pillar between the trench and the first fin, wherein:
the first semiconductor fin nub has a first height,
the first semiconductor pillar has a second height different than the first height, and
the first fin has a third height different than the first height and the second height.
7. The semiconductor arrangement of claim 6 , wherein:
the second height is less than third height and greater than the first height.
8. A semiconductor arrangement, comprising:
a first fin protruding from a substrate;
an alignment mark overlying the substrate; and
a dielectric layer between the first fin and the alignment mark and overlying a first portion of the alignment mark, wherein an uppermost surface of a second portion of the alignment mark between the first portion of the alignment mark and the first fin is above the dielectric layer.
9. The semiconductor arrangement of claim 8 , comprising:
an oxide layer overlying the second portion of the alignment mark; and
a gate structure overlying the oxide layer.
10. The semiconductor arrangement of claim 8 , wherein:
an uppermost surface of a third portion of the alignment mark is above the dielectric layer, and
the first portion of the alignment mark is between the second portion of the alignment mark and the third portion of the alignment mark.
11. The semiconductor arrangement of claim 8 , comprising:
a first semiconductor fin nub protruding from the substrate, wherein the dielectric layer overlies the first semiconductor fin nub.
12. The semiconductor arrangement of claim 8 , wherein:
the substrate defines a trench,
the first fin is between the alignment mark and the trench, and
the dielectric layer is disposed in the trench.
13. The semiconductor arrangement of claim 8 , comprising:
a first semiconductor pillar protruding from the substrate, wherein:
the first fin has a first height,
the first semiconductor pillar has a second height less than the first height,
the first fin is between the first semiconductor pillar and the alignment mark, and
the dielectric layer overlies the first semiconductor pillar.
14. A semiconductor arrangement, comprising:
a first semiconductor fin nub protruding from a substrate;
a first semiconductor pillar protruding from the substrate;
a first fin protruding from the substrate; and
a dielectric layer over the first semiconductor fin nub and the first semiconductor pillar, wherein:
an uppermost surface of the first fin is above the dielectric layer,
a trench is defined in the substrate between the first semiconductor fin nub and the first semiconductor pillar,
the dielectric layer is disposed in the trench,
the dielectric layer has a first depth at a location vertically aligned with the trench,
the dielectric layer has a second depth at a location vertically aligned with the first semiconductor fin nub,
the dielectric layer has a third depth at a location vertically aligned with the first semiconductor pillar,
the first depth is greater than the second depth and the third depth, and
the second depth is greater than the third depth.
15. The semiconductor arrangement of claim 14 , comprising:
an alignment mark overlying the substrate, wherein the dielectric layer overlies a first portion of the alignment mark and an uppermost surface of a second portion of the alignment mark is above the dielectric layer.
16. The semiconductor arrangement of claim 14 , wherein the first semiconductor fin nub and the first semiconductor pillar have a same material composition.
17. The semiconductor arrangement of claim 14 , wherein:
the first semiconductor fin nub has a first height, and
the first semiconductor pillar has a second height greater than the first height.
18. The semiconductor arrangement of claim 14 , comprising:
a gate, wherein the dielectric layer overlies the first semiconductor fin nub and underlies the gate.
19. The semiconductor arrangement of claim 18 , wherein the gate overlies the first fin.
20. The semiconductor arrangement of claim 14 , comprising:
an alignment mark overlying the substrate, wherein the dielectric layer is between the first fin and the alignment mark and overlies a first portion of the alignment mark.