Multiple fin heights for effective width tuning
Embodiments of the present disclosure are directed to co-integrating multiple fin heights with bottom dielectric isolations for effective width tuning. In a non-limiting embodiment, a semiconductor structure includes a first shallow trench isolation (STI) region formed over a first portion of a substrate and a second STI region formed over a second portion of the substrate. A topmost surface of the second STI region is coplanar to a topmost surface of the first STI region. A first fin is formed in the first STI region and a second fin is formed in the second STI region. A topmost surface of the second fin is coplanar to a topmost surface of the first fin. A bottom dielectric isolation (BDI) region is positioned between the first fin and the substrate, thereby providing a first effective width and a second effective width for the first fin and second fin, respectively.
1 . A semiconductor structure comprising:
a first shallow trench isolation (STI) region formed over a first portion of a substrate;
a second STI region formed over a second portion of the substrate, wherein a topmost surface of the second STI region is coplanar to a topmost surface of the first STI region;
a first fin formed in and above the first STI region;
a second fin formed in and above the second STI region, wherein a topmost surface of the second fin is coplanar to a topmost surface of the first fin; and
a bottom dielectric isolation (BDI) region positioned directly between the first fin and the substrate, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
2 . The semiconductor structure of claim 1 , wherein the BDI region is directly on the topmost surface of the first STI region.
3 . The semiconductor structure of claim 1 , further comprising an air gap within the BDI region.
4 . The semiconductor structure of claim 1 , further comprising a first source/drain (S/D) region in direct contact with the second fin and a second S/D region in direct contact with the first fin.
5 . The semiconductor structure of claim 4 , wherein the second S/D region is directly on the BDI region.
6 . A semiconductor structure comprising:
a substrate comprising an n-type region and a p-type region;
a first fin formed over the n-type region of the substrate;
a second fin formed over the p-type region of the substrate;
a first bottom dielectric isolation (BDI) region positioned directly between the first fin and the n-type region of the substrate; and
a second BDI region positioned directly between the second fin and the p-type region of the substrate, wherein a height of the second BDI region is different than a height of the first BDI region, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
7 . The semiconductor structure of claim 6 , wherein the first BDI region is directly on the n-type region of the substrate and the second BDI region is directly on the p-type region of the substrate.
8 . The semiconductor structure of claim 6 , further comprising an air gap within at least one of the first BDI region and the second BDI region.
9 . The semiconductor structure of claim 6 , further comprising a first source/drain (S/D) region in direct contact with the second fin and a second S/D region in direct contact with the first fin.
10 . The semiconductor structure of claim 9 , wherein the first S/D region is directly on the second BDI region and the second S/D region is directly on the first BDI region.
11 . A semiconductor structure comprising:
a plurality of fins formed over a substrate, the plurality of fins comprising a first fin comprising a first height, a second fin comprising a second height different than the first height, and a third fin comprising a third height different than the first height and the second height;
a gate formed over the first fin, the second fin, and the third fin;
a first bottom dielectric isolation (BDI) region positioned directly between the first fin and the substrate;
a second BDI region positioned directly between the second fin and the substrate; and
a third BDI region positioned directly between the third fin and the substrate;
wherein an effective width of the first fin is less than an effective width of the second fin and the effective width of the second fin is less than an effective width of the third fin.
12 . The semiconductor structure of claim 11 , wherein topmost surfaces of each fin of the plurality of fins are coplanar.
13 . The semiconductor structure of claim 11 , further comprising an air gap within at least one of the first BDI region, the second BDI region, and the third BDI region.
14 . The semiconductor structure of claim 11 , wherein a height of the first BDI region is greater than a height of the second BDI region and the height of the second BDI region is greater than a height of the third BDI region.
15 . A method for forming a semiconductor device, the method comprising:
forming a first shallow trench isolation (STI) region over a first portion of a substrate;
forming a second STI region over a second portion of the substrate, wherein a topmost surface of the second STI region is coplanar to a topmost surface of the first STI region;
forming a first fin in and above the first STI region;
forming a second fin in and above the second STI region, wherein a topmost surface of the second fin is coplanar to a topmost surface of the first fin; and
forming a bottom dielectric isolation (BDI) region directly between the first fin and the substrate, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
16 . The method of claim 15 , wherein the BDI region is directly on the topmost surface of the first STI region.
17 . The method of claim 15 , further comprising forming an air gap within the BDI region.
18 . The method of claim 15 , further comprising forming a first source/drain (S/D) region in direct contact with the second fin and a second S/D region in direct contact with the first fin.
19 . The method of claim 18 , wherein the second S/D region is directly on the BDI region.
20 . A method for forming a semiconductor device, the method comprising:
forming a substrate comprising an n-type region and a p-type region;
forming a first fin over the n-type region of the substrate;
forming a second fin over the p-type region of the substrate;
forming a first bottom dielectric isolation (BDI) region directly between the first fin and the n-type region of the substrate; and
forming a second BDI region directly between the second fin and the p-type region of the substrate, wherein a height of the second BDI region is different than a height of the first BDI region, thereby providing the first fin having a first effective width and the second fin having a second effective width different than the first effective width.
21 . The method of claim 20 , wherein the first BDI region is directly on the n-type region of the substrate and the second BDI region is directly on the p-type region of the substrate.
22 . The method of claim 20 , further comprising forming an air gap within at least one of the first BDI region and the second BDI region.
23 . The method of claim 20 , further comprising forming a first source/drain (S/D) region in direct contact with the second fin and a second S/D region in direct contact with the first fin.
24 . The method of claim 23 , wherein the first S/D region is directly on the second BDI region and the second S/D region is directly on the first BDI region.