3D semiconductor device and structure
A semiconductor device including: a silicon layer including a single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level and has a diameter of less than 450 nm, where the second level thickness is less than four microns, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.
1. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon and a plurality of first transistors;
a first metal layer disposed over said first silicon layer;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said third metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer; and
a via disposed through said second level,
wherein said via has a diameter of less than 450 nm,
wherein said second level thickness is less than four microns,
wherein said fifth metal layer comprises a global power distribution grid, and
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said second metal layer by at least 50%.
2. The device according to claim 1 ,
wherein said via comprises tungsten.
3. The device according to claim 1 ,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
4. The device according to claim 1 ,
wherein at least one of said plurality of second transistors comprises a metal gate.
5. The device according to claim 1 ,
wherein a typical thickness of said second metal layer is greater than a typical thickness of said third metal layer by at least 50%.
6. The device according to claim 1 ,
wherein at least one of said plurality of second transistors is a vertically oriented transistor.
7. The device according to claim 1 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises at least a part of said second metal layer.
8. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon and a plurality of first transistors;
a first metal layer disposed over said first silicon layer;
a second metal layer disposed over said first metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said second metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error; and
a via disposed through said second level,
wherein said via comprises tungsten,
wherein said fifth metal layer comprises a global power distribution grid, and
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said second metal layer by at least 50%.
9. The device according to claim 8 ,
wherein said via has a diameter of less than 450 nm.
10. The device according to claim 8 ,
wherein said second level thickness is less than four microns.
11. The device according to claim 8 ,
wherein at least one of said plurality of second transistors comprises a metal gate.
12. The device according to claim 8 , further comprising:
a third metal layer disposed between said second metal layer and said second level,
wherein a typical thickness of said second metal layer is greater than a typical thickness of said third metal layer by at least 50%.
13. The device according to claim 8 ,
wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain comprise a same doping type.
14. The device according to claim 8 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises at least a portion of said second metal layer.
15. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon and a plurality of first transistors;
a first metal layer disposed over said first silicon layer;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said third metal layer,
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error; and
a via disposed through said second level,
wherein at least one of said plurality of second transistors comprises a metal gate,
wherein a typical thickness of said second metal layer is greater than a typical thickness of said third metal layer by at least 50%,
wherein said fifth metal layer comprises a global power distribution grid, and
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said second metal layer by at least 50%.
16. The device according to claim 15 ,
wherein said via comprises tungsten.
17. The device according to claim 15 ,
wherein said second level thickness is less than four microns.
18. The device according to claim 15 ,
wherein said via has a diameter of less than 450 nm.
19. The device according to claim 15 ,
wherein at least one of said plurality of second transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain comprise a same doping type.
20. The device according to claim 15 , further comprising:
a power delivery path to at least one of said plurality of second transistors,
wherein said power delivery path comprises at least a portion of said second metal layer.