3D memory semiconductor devices and structures with bit-line pillars
A 3D memory device, the device comprising: a plurality of memory cells, wherein each memory cell of said plurality of memory cells comprises at least one memory transistor, wherein each of said at least one memory transistor comprises a source, a drain, and a channel; a plurality of bit-line pillars, wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain, wherein said bit-line pillars are vertically oriented, wherein said channel is horizontally oriented, wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device.
1. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
a plurality of bit-line pillars,
wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein said bit-line pillars are vertically oriented,
wherein said channel is horizontally oriented,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain, and
wherein said plurality of bit-line pillars comprise a thermally conductive path from said plurality of memory cells to an external surface of said device.
2. The device according to claim 1 ,
wherein each memory cell of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
3. The device according to claim 1 ,
wherein said channel comprises a circular shape or an ellipsoidal shape.
4. The device according to claim 1 , further comprising:
a level of memory control circuits,
wherein said level of memory control circuits is disposed either above or below said plurality of memory cells.
5. The device according to claim 1 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
6. The device according to claim 1 ,
wherein said channel is isolated from another channel disposed directly above said channel.
7. The device according to claim 1 ,
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following the same lithography step.
8. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel; and
a plurality of bit-line pillars,
wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein said plurality of bit-line pillars are vertically oriented,
wherein said channel is horizontally oriented,
wherein a plurality of said channels has been recrystallized, and
wherein said recrystallized was initiated from said source and/or said drain.
9. The device according to claim 8 ,
wherein each memory cell of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
10. The device according to claim 8 ,
wherein each of said at least one memory transistor is directly connected to at least one of said plurality of bit-line pillars.
11. The device according to claim 8 ,
wherein said channel comprises a channel width greater than 5 nm and less than 25 nm.
12. The device according to claim 8 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
13. The device according to claim 8 ,
wherein said plurality of memory cells are organized as at least four independently controlled memory arrays.
14. The device according to claim 8 ,
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step.
15. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a drain, and a channel; and
a plurality of bit-line pillars,
wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein said bit-line pillars are vertically oriented, and
wherein said channel is horizontally oriented; and
a memory controller circuit,
wherein said memory controller circuit is capable of providing a word-line hold voltage, and
wherein said word-line hold voltage extends retention of said plurality of memory cells.
16. The device according to claim 15 ,
wherein each memory cell of said plurality of memory cells comprises a charge trap memory,
wherein said channel comprises polysilicon,
wherein said source and/or said drain comprises metal atoms, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
17. The device according to claim 15 ,
wherein each of said at least one memory transistor is directly connected to at least one of said plurality of bit-line pillars.
18. The device according to claim 15 ,
wherein said plurality of memory cells comprise a partially or fully metalized source, and/or, a partially or fully metalized drain.
19. The device according to claim 15 ,
wherein at least one of said plurality of said memory cells comprise a tunneling oxide thinner than 1 nm.
20. The device according to claim 15 ,
wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step.