Multi-resistance MRAM
Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.
1. An apparatus comprising:
a magnetoresistive random access memory (MRAM) die, the MRAM die comprising a plurality of memory cells, a memory cell comprising a fixed layer, a barrier layer, and a free layer, the barrier layer disposed between the fixed layer and the free layer, the free layer comprising:
a wall extension region configured to provide a plurality of resistance states for the memory cell corresponding to positions of a magnetic domain wall within the wall extension region; and
an end region configured to exclude the domain wall.
2. The apparatus of claim 1 , further comprising a domain stabilization layer coupled to the end region of the free layer, the domain stabilization layer configured to stabilize a magnetization direction for the end region of the free layer.
3. The apparatus of claim 2 , wherein the domain stabilization layer comprises an antiferromagnetic layer.
4. The apparatus of claim 3 , wherein the antiferromagnetic layer is configured to induce a unidirectional magnetic anisotropy in a portion of the free layer.
5. The apparatus of claim 2 , wherein the domain stabilization layer comprises a multilayer.
6. The apparatus of claim 5 , wherein the multilayer comprises one or more of: a cobalt/platinum multilayer and a cobalt/palladium multilayer.
7. The apparatus of claim 5 , wherein the multilayer is configured to induce a coercivity increase in a portion of the free layer.
8. The apparatus of claim 2 , wherein the domain stabilization layer is configured to prevent migration of the domain wall into a portion of the free layer by stabilizing a magnetization direction for the portion of the free layer.
9. The apparatus of claim 2 , further comprising a second domain stabilization layer configured to prevent migration of the domain wall into a second portion of the free layer, wherein the free layer comprises an elongate arm comprising a plurality of pinning sites for pinning the domain wall, the portion of the free layer comprises a first end portion of the arm, and the second portion of the free layer comprises a second end portion of the arm opposite to the first end portion.
10. The apparatus of claim 1 , wherein the free layer comprises:
a nucleation region configured to form the magnetic domain wall; and
an arm extending from the nucleation region, the arm comprising a plurality of pinning sites for pinning the domain wall.
11. The apparatus of claim 1 , further comprising a controller configured to increase the resistance state of a selected one of the memory cells by applying a first write current to move the domain wall in a first direction.
12. The apparatus of claim 11 , wherein the controller is further configured to decrease the resistance state of the selected one of the memory cells by applying a second write current in a direction opposite to the first write current, to move the domain wall in a second direction opposite to the first direction.
13. The apparatus of claim 1 , wherein the free layer further comprises a nucleation region configured to form the magnetic domain wall in response to a write current.
14. The apparatus of claim 13 , further comprising a controller configured to apply the write current to a selected one of the memory cells.
15. The apparatus of claim 13 , further comprising a plurality of pinning sites formed at predetermined locations in the wall extension region and configured to pin the domain wall such that the domain wall migrates from one pinning site to another pinning site in response to a changed write current.
16. The apparatus of claim 12 , wherein the controller is further configured to, subsequent to applying the second write current, increase the resistance state of the selected one of the memory cells by applying a third write current in the direction of the first write current to move the domain wall in the first direction.
17. The apparatus of claim 16 , wherein the controller is further configured to apply the third write current to move the domain wall without applying an erase current.
18. The apparatus of claim 1 , wherein the memory cells are configured to store weights of a neural network.
19. The apparatus of claim 18 , further comprising a controller configured to:
receive a plurality of inputs apply a plurality of inputs for a neural network;
perform a multiplication of the inputs with the weights of the neural network stored in the memory cells; and
perform a summation of results of the multiplication.