Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

1. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

an array of memory opening fill structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced apart along a second horizontal direction, wherein each of the memory opening fill structures comprises a memory film and a memory-level channel portion;

an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, wherein each of the drain-select-level assemblies comprises a drain-select-level channel portion contacting a respective memory-level channel portion, a drain region contacting an upper end of the drain-select-level channel portion, and a gate dielectric laterally surrounding the drain-select-level channel portion;

a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies; and

a drain-select-level isolation strip comprising an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion that laterally surrounds a second set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies,

wherein the isolation dielectric has a same material composition and a same thickness as each of the gate dielectrics.

2. The three-dimensional memory device of claim 1 , wherein the drain-select-level isolation strip further comprises a semiconductor material strip that is located above the isolation dielectric.

3. The three-dimensional memory device of claim 2 , wherein each of the drain-select-level channel portions has a same material composition as the semiconductor material strip.

4. The three-dimensional memory device of claim 3 , wherein the semiconductor material strip has a same width as the isolation dielectric.

5. The three-dimensional memory device of claim 2 , wherein top surfaces of the drain regions are located within a horizontal plane including a top surface of the semiconductor material strip.

6. The three-dimensional memory device of claim 5 , wherein top surfaces of the gate dielectrics are located above a top surface of the isolation dielectric and within the horizontal plane including the top surface of the semiconductor material strip.

7. The three-dimensional memory device of claim 1 , wherein the isolation dielectric comprises:

a pair of sidewall portions that laterally extend along the first horizontal direction with a lateral undulation along the second horizontal direction; and

a planar portion having a planar bottom surface, laterally extending along the first horizontal direction, and adjoined to bottom peripheries of the pair of sidewall segments.

8. The three-dimensional memory device of claim 7 , wherein each of the sidewall portions comprises a laterally alternating sequence of laterally-concave vertical surface segments and laterally-convex vertical surface segments.

9. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

an array of memory opening fill structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced apart along a second horizontal direction, wherein each of the memory opening fill structures comprises a memory film and a memory-level channel portion;

an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, wherein each of the drain-select-level assemblies comprises a drain-select-level channel portion contacting a respective memory-level channel portion, a drain region contacting an upper end of the drain-select-level channel portion, and a gate dielectric laterally surrounding the drain-select-level channel portion;

a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies;

a drain-select-level isolation strip comprising an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion that laterally surrounds a second set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies; and

an etch stop dielectric layer overlying the alternating stack, wherein each drain-select-level assembly of the array of drain-select-level assemblies vertically extends through a respective opening in the etch stop dielectric layer, and the isolation dielectric extends through an opening in the etch stop dielectric layer.

10. A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

an array of memory opening fill structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced apart along a second horizontal direction, wherein each of the memory opening fill structures comprises a memory film and a memory-level channel portion;

an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, wherein each of the drain-select-level assemblies comprises a drain-select-level channel portion contacting a respective memory-level channel portion, a drain region contacting an upper end of the drain-select-level channel portion, and a gate dielectric laterally surrounding the drain-select-level channel portion;

a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies; and

a drain-select-level isolation strip comprising an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion that laterally surrounds a second set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies,

wherein each drain-select-level assembly of the array of drain-select-level assemblies comprises a drain-select-level dielectric core laterally surrounded by a respective one of the drain-select-level channel portions.