3D semiconductor device and structure with single-crystal layers
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein said first transistors each comprises a single crystal channel;
first metal layers interconnecting at least said first transistors;
a second metal layer overlaying said first metal layers; and
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein said second level overlays said first level,
wherein said second transistors each comprises at least two side-gates,
wherein said second level is directly bonded to said first level, and
wherein said bonded comprises direct oxide to oxide bonds.
2. The device according to claim 1 ,
wherein said first level comprises alignment marks, and
wherein said second transistors are aligned to said alignment marks with a less than 40 nm alignment error.
3. The device according to claim 1 ,
wherein said at least two side-gates each comprises a metal gate structure.
4. The device according to claim 1 ,
wherein at least one of said second transistors is an N-type transistor, and
wherein at least one of said second transistors is a P-type transistor.
5. The device according to claim 1 ,
wherein said first level comprises third transistors and fourth transistors,
wherein said fourth transistors are overlying said third transistors, and
wherein said third transistors and said fourth transistors are self-aligned, being processed following a same lithography step.
6. The device according to claim 1 ,
wherein said bonded additionally comprises direct metal to metal bonds that are disposed on a same level as the direct oxide to oxide bonds.
7. The device according to claim 1 ,
wherein said first level comprises a memory array, and
wherein said second level comprises control circuits for controlling said memory array.
8. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising alignment marks;
first transistors overlaying said first single crystal layer;
second transistors overlaying said first transistors; and
a second level comprising a second single crystal layer, said second level comprising said second transistors,
wherein said second level overlays said first level,
wherein said second transistors each comprises hafnium oxide,
wherein said second level is directly hybrid bonded to said first level,
wherein said bonded comprises direct oxide to oxide bonds, and
wherein said bonded additionally comprises direct metal to metal bonds that are disposed on a same level as the direct oxide to oxide bonds.
9. The device according to claim 8 ,
wherein each of said second transistors comprises a source, a channel, and a drain, and
wherein said source, said channel, and said drain have a similar doping type.
10. The device according to claim 8 ,
wherein said second transistors each comprises a metal gate structure.
11. The device according to claim 8 ,
wherein each of said second transistors are horizontally oriented, and
wherein each of said second transistors comprises at least two side-gates each comprising the hafnium oxide.
12. The device according to claim 8 , further comprising:
a third level comprising a third single crystal layer,
wherein said third level overlays said second level.
13. The device according to claim 8 , further comprising:
wherein said first level comprises third transistors and fourth transistors,
wherein said fourth transistors are overlying said third transistors, and
wherein said third transistors and said fourth transistors are self-aligned, being processed following a same lithography step.
14. The device according to claim 8 ,
wherein said device comprises an array of memory cells,
wherein each of said memory cells comprises at least two of said second transistors, and
wherein said first level comprises a periphery control circuit to control said array of memory cells.
15. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein said first transistors each comprises a single crystal channel;
first metal layers interconnecting at least said first transistors;
second transistors overlaying said first transistors, and
a second level comprising a second single crystal layer, said second level comprising said second transistors,
wherein said second level overlays said first level,
wherein said second transistors each comprises a raised source and a raised drain,
wherein said second level is directly bonded to said first level, and
wherein said bonded comprises direct metal to metal bonds.
16. The device according to claim 15 ,
wherein said third transistors each comprises at least two side gates.
17. The device according to claim 15 ,
wherein said second transistors each comprises a hafnium oxide gate dielectric layer and a metal gate structure.
18. The device according to claim 15 ,
wherein each of said second transistors comprises the raised source, a channel, and the raised drain, and
wherein said source, said channel, and said drain have a similar doping type.
19. The device according to claim 15 ,
wherein said bonded additionally comprises direct oxide to oxide bonds that are disposed on a same level as the direct metal to metal bonds.
20. The device according to claim 15 ,
wherein said second level comprises a memory array, and
wherein said first level comprises control circuits to control data written to said memory array.