Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.
1. A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming peripheral circuitry in and/or on said first level,
wherein said peripheral circuitry comprises first single crystal transistors;
forming a first metal layer on top of said first level;
forming a second metal layer on top of said first metal layer;
forming at least one second level disposed on top of or above said second metal layer;
performing a first lithography step on said second level;
forming at least one third level disposed on top of or above said at least one second level; and then
performing a second lithography step on said third level;
performing additional processing steps to form a plurality of first memory cells within said at least one second level and a plurality of second memory cells within said at least one third level,
wherein said additional processing steps comprise deposition processes and etch processes,
wherein each of said plurality of first memory cells comprises at least one second transistor,
wherein each of said plurality of second memory cells comprises at least one third transistor; and then
performing at least one deposition step to simultaneously deposit gate electrodes on both said second transistors and said third transistors.
2. The method according to claim 1 , further comprising:
forming a third metal layer disposed on top of or above said at least one third level; and
forming a through layer via (TLV) connecting said third metal layer to said second metal layer,
wherein a diameter of said through layer via is less than about 400 nm.
3. The method according to claim 1 , further comprising:
forming at least two overlying layers each comprising different materials,
wherein said second level comprises said at least two overlaying layers, and
wherein said different materials comprise different etch rates and are selectively etch-able with respect to each other.
4. The method according to claim 1 ,
wherein said performing at least one deposition step comprises using Atomic Layer Deposition (ALD).
5. The method according to claim 1 ,
wherein said gate electrode comprises metal.
6. The method according to claim 1 ,
wherein said second metal layer comprises tungsten.
7. The method according to claim 1 ,
wherein forming said peripheral circuitry comprises using a weaker anneal process in consideration of subsequent thermal processing.
8. A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming peripheral circuitry in and/or on said first level,
wherein said peripheral circuitry comprises first single crystal transistors;
forming a first metal layer on top of said first level;
forming a second metal layer on top of said first metal layer;
forming at least one second level disposed on top of or above said second metal layer;
performing a first lithography step on said second level;
forming at least one third level disposed on top of or above said at least one second level;
performing a second lithography step on said third level;
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein said additional processing steps comprise deposition processes and etch processes,
wherein each of said plurality of first memory cells comprises at least one second transistor,
wherein each of said plurality of second memory cells comprises at least one third transistor; and then
performing a deposition step to simultaneously deposit gate electrodes on both said at least one second transistor and said at least one third transistor.
9. The method according to claim 8 , further comprising:
forming a third metal layer disposed on top of said third level; and
forming a through layer via (TLV) connecting said third metal layer to said second metal layer,
wherein a diameter of said through layer via is less than about 400 nm.
10. The method according to claim 8 , further comprising:
forming at least two overlying layers each comprising different materials,
wherein said second level comprises said at least two overlaying layers, and
wherein said different materials comprise different etch rates and are selectively etch-able with respect to each other.
11. The method according to claim 8 ,
wherein said performing a deposition step comprises using Atomic Layer Deposition (ALD).
12. The method according to claim 8 ,
wherein said gate electrode comprises tungsten.
13. The method according to claim 8 ,
wherein said second metal layer comprises tungsten.
14. The method according to claim 8 ,
wherein forming said peripheral circuitry comprises using a weaker anneal process in consideration of subsequent thermal processing.
15. A method for producing a 3D semiconductor device, the method comprising:
providing a first level, said first level comprising a first single crystal layer;
forming peripheral circuitry in and/or on said first level,
wherein said peripheral circuitry comprises first single crystal transistors;
forming a first metal layer on top of said first level;
forming a second metal layer on top of said first metal layer;
forming at least one second level disposed on top of or above said second metal layer;
performing a first lithography step on said second level;
forming at least one third level disposed on top of or above said second level;
performing a second lithography step on said third level;
performing a first set of additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein said additional processing steps comprise deposition processes and etch processes,
wherein each of said plurality of first memory cells comprises at least one second transistor, and
wherein each of said plurality of second memory cells comprises at least one third transistor; and then
performing a deposition step to simultaneously deposit gate electrodes on both said at least one second transistor and said at least one third transistor,
wherein said gate electrodes comprise metal.
16. The method according to claim 15 , further comprising:
forming a third metal layer disposed on top of said third level; and
forming a through layer via (TLV) connecting said third metal layer to said second metal layer,
wherein a diameter of said through layer via is less than about 400 nm.
17. The method according to claim 15 , further comprising:
forming at least two overlying layers each comprising different materials,
wherein said second level comprises said at least two overlaying layers, and
wherein said different materials comprise different etch rates and are selectively etch-able with respect to each other.
18. The method according to claim 15 ,
wherein said performing a first set of additional processing steps comprises using Atomic Layer Deposition (ALD).
19. The method according to claim 15 ,
wherein said metal gate electrodes comprise tungsten.
20. The method according to claim 15 ,
wherein forming said peripheral circuitry comprises using a weaker anneal process in consideration of subsequent thermal processing.