Semiconductor device including trimmed-gates and method of forming same

1. A semiconductor device comprising:

first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially orthogonal to the first direction; and

gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and

for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and

when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are of extending into the gap.

2. The semiconductor device of claim 1 , wherein:

for a functional intersection at which a corresponding given one of the gate structures crosses over a corresponding given one of the first or second active regions and for which the given gate structure is functionally connected to the given active region, an extension of the given gate structure extends a predetermined distance in the second direction beyond the given active region and into the gap.

3. The semiconductor device of claim 2 , wherein:

a height H EXT in the second direction of the extension of the gate structure is less than or equal to about a three times multiple of a width WG in the first direction of the gate structure, wherein:

H EXT ≤(≈3W G ).

4. The semiconductor device of claim 1 , wherein:

each of the first and second active regions is configured for finFET technology.

5. The semiconductor device of claim 1 , further comprising:

at least one component of a circuit positioned within the gap.

6. The semiconductor device of claim 1 , further comprising:

over the gap, one or more metal lines in one or more corresponding metallization layers.

7. The semiconductor device of claim 6 , wherein:

at least some of the one or more metal lines represent portions of a power grid.

8. The semiconductor device of claim 1 , wherein:

each of the gate structures which corresponds to one of the notches in the notched profile is functionally coupled to the corresponding one of the first and second active regions.

9. The semiconductor device of claim 1 , wherein:

each of the gate structures which does not correspond to one of the notches in the notched profile is functionally coupled to the corresponding one of the first and second active regions.

10. A method of manufacturing a semiconductor device, the method comprising:

forming first and second active regions extending in a first direction and separated by a gap;

forming gate structures correspondingly over the first and second active regions, the gate structures extending in a second direction, the second direction being substantially orthogonal to the first direction; and

removing central regions of the gate structures, a portion of each of some but not all remnant gate structures (gate extension) extending partially into the gap such that, when viewing the remnant gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the remnant gate structures which are extending into the gap.

11. The method of claim 10 , wherein the forming first and second active regions further includes:

forming at least one component of a semiconductor integrated circuit (IC) in a corresponding at least one of the first and second active regions.

12. The method of claim 10 , wherein the forming gate structures further includes:

at an intersection between a corresponding one of the first and second active regions and a corresponding one of the gate structures that is designated to be functional (functional intersection), making a functional connection between the corresponding one of the first and second active regions and the corresponding one of the gate structures.

13. The method of claim 12 , wherein:

the forming first and second active regions further includes:

locating intra-gap segments of the gate structures correspondingly over the gap; and

arranging each intra-gap segment to include two end regions separated by a central region;

each of the end regions extends a corresponding overhang distance in the second direction from the corresponding one of the first and second active regions towards the corresponding one of the central regions of the intra-gap segments;

the intra-gap segments abut corresponding functional intersections; and

for each end region of the intra-gap segments, the corresponding overhang distance is approximately equal to a predetermined value which facilitates making a functional connection between the corresponding one of the first and second active regions and the corresponding one of the gate structures.

14. The method of claim 13 , wherein:

each of the gate structures has substantially a same width in the first direction; and

the predetermined value is less than or equal to about a three times multiple of the width of the gate structures.

15. The method of claim 13 , wherein:

each of the gate structures has substantially a same width in the first direction; and

the predetermined value is greater than of the width of the gate structures.

16. The method of claim 15 , further comprising:

over locations formerly corresponding to the central regions of the intra-gap segments, forming one or more metal lines in one or more corresponding metallization layers.

17. The method of claim 16 , wherein:

at least some of the one or more metal lines represent portions of a power grid.

18. A semiconductor device comprising:

first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially orthogonal to the first direction; and

gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and

for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and

when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are extending into the gap; and

each of the gate structures which corresponds to one of the notches in the notched profile being functionally coupled to the corresponding one of the first and second active regions.

19. The semiconductor device of claim 18 , wherein:

each of the gate structures which does not correspond to one of the notches in the notched profile is functionally coupled to the corresponding one of the first and second active regions at a corresponding functional intersection.

20. The semiconductor device of claim 19 , wherein:

for each functional intersection at which a corresponding given one of the gate structures crosses over a corresponding one of the first or second active regions and for which the given gate structure is functionally connected to the given active region, an extension of the giv ate structure extends a predetermined distance in the second direction beyond the given active region and into the gap.