3D semiconductor device and structure with bonding
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein each of said first transistors comprises a single crystal channel;
first metal layers interconnecting at least said first transistors;
a second metal layer overlaying said first metal layers;
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein said second level overlays said first level,
wherein said second level comprises a plurality of first DRAM memory cells,
wherein each of said plurality of first DRAM memory cells comprises at least one of said second transistors; and
a third level comprising a third single crystal layer, said third level comprising third transistors,
wherein said third level overlays said second level,
wherein said third level comprises a plurality of second DRAM memory cells,
wherein each of said plurality of second DRAM memory cells comprises at least one of said third transistors, and
wherein said third level is directly bonded to said second level.
2. The device according to claim 1 ,
wherein said first level comprises a first power line charged to a first voltage,
wherein said second level comprises a second power line charged to a second voltage, and
wherein said second voltage is greater than said first voltage by at least 50%.
3. The device according to claim 1 ,
wherein said device was singulated using laser dicing equipment.
4. The device according to claim 1 ,
wherein said bonded comprises direct oxide-to-oxide bonds.
5. The device according to claim 1 ,
wherein said second transistors are aligned to said first transistors with a less than 400 nm alignment error.
6. The device according to claim 1 ,
wherein said bonded comprises metal-to-metal bonds and oxide-to-oxide bonds.
7. The device according to claim 1 ,
wherein at least one of said first transistors controls power delivery for at least one of said second transistors.
8. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein each of said first transistors comprises a single crystal channel;
first metal layers interconnecting at least said first transistors;
a second metal layer overlaying said first metal layers;
a second level comprising second transistors,
wherein said second level overlays said first level,
wherein said second level comprises a plurality of first DRAM memory cells, and
wherein each of said plurality of first DRAM memory cells comprises at least one of said second transistors;
a third level comprising third transistors,
wherein said third level overlays said second level,
wherein said third level comprises a plurality of second DRAM memory cells, and
wherein each of said plurality of second DRAM memory cells comprises at least one of said third transistors; and
a fourth level comprising fourth transistors,
wherein said fourth level overlays said third level,
wherein said fourth level comprises a plurality of third DRAM memory cells, and
wherein each of said plurality of third DRAM memory cells comprises at least one of said fourth transistors, and
wherein said third level is directly bonded to said second level.
9. The device according to claim 8 ,
wherein said device comprises singulation using laser dicing equipment.
10. The device according to claim 8 ,
wherein said bonded comprises direct oxide-to-oxide bonds.
11. The device according to claim 5 ,
wherein said second transistors are aligned to said first transistors with a less than 400 nm alignment error.
12. The device according to claim 8 ,
wherein said bonded comprises metal-to-metal bonds.
13. The device according to claim 8 ,
wherein at least one of said first transistors controls power delivery for at least one of said second transistors.