Field effect transistors with gate fins and method of making the same
A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.
1. A semiconductor structure, comprising:
a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a first transistor active region that is a portion of the semiconductor substrate; and
a first field effect transistor comprising:
at least one line trench extending downward from a top surface of the first transistor active region, laterally extending along a first horizontal direction, and located within the first transistor active region;
a channel region comprising a portion of the first transistor active region that laterally surrounds or underlies the at least one line trench;
a gate dielectric contacting all surfaces of the at least one line trench and comprising a planar gate dielectric portion that extends over an entirety of a top surface of the channel region;
a gate electrode comprising a planar gate electrode portion that overlies the planar gate dielectric portion and at least one gate electrode fin portion located within the at least one line trench; and
a source region and a drain region located in the semiconductor substrate and laterally spaced from each other by the channel region;
wherein the planar gate dielectric portion comprises a pair of sidewalls that laterally extend along the first horizontal direction and contacting a respective sidewall segment of the shallow trench isolation structure.
2. A semiconductor structure, comprising:
a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a first transistor active region that is a portion of the semiconductor substrate; and
a first field effect transistor comprising:
at least one line trench extending downward from a top surface of the first transistor active region, laterally extending along a first horizontal direction, and located within the first transistor active region;
a channel region comprising a portion of the first transistor active region that laterally surrounds or underlies the at least one line trench;
a gate dielectric contacting all surfaces of the at least one line trench and comprising a planar gate dielectric portion that extends over an entirety of a top surface of the channel region;
a gate electrode comprising a planar gate electrode portion that overlies the planar gate dielectric portion and at least one gate electrode fin portion located within the at least one line trench; and
a source region and a drain region located in the semiconductor substrate and laterally spaced from each other by the channel region;
wherein the planar gate electrode portion comprises a vertical stack including:
a planar semiconductor gate electrode portion that is adjoined to the at least one gate electrode fin portion; and
a planar metallic gate electrode portion that overlies the planar semiconductor gate electrode portion; and
wherein a top surface of the planar semiconductor gate electrode portion is located within a horizontal plane including a top surface of the shallow trench isolation structure.
3. A semiconductor structure, comprising:
a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a first transistor active region that is a portion of the semiconductor substrate; and
a first field effect transistor comprising:
at least one line trench extending downward from a top surface of the first transistor active region, laterally extending along a first horizontal direction, and located within the first transistor active region;
a channel region comprising a portion of the first transistor active region that laterally surrounds or underlies the at least one line trench;
a gate dielectric contacting all surfaces of the at least one line trench and comprising a planar gate dielectric portion that extends over an entirety of a top surface of the channel region;
a gate electrode comprising a planar gate electrode portion that overlies the planar gate dielectric portion and at least one gate electrode fin portion located within the at least one line trench; and
a source region and a drain region located in the semiconductor substrate and laterally spaced from each other by the channel region;
wherein the planar gate electrode portion comprises a vertical stack including:
a planar semiconductor gate electrode portion that is adjoined to the at least one gate electrode fin portion; and
a planar metallic gate electrode portion that overlies the planar semiconductor gate electrode portion;
wherein:
the planar metallic gate electrode portion has a same lateral extent as the planar semiconductor gate electrode portion along the first horizontal direction; and
the planar metallic gate electrode portion has a greater lateral extent than the planar semiconductor gate electrode portion along a second horizontal direction that is perpendicular to the first horizontal direction and contacts surface segments of a top surface of the shallow trench isolation structure.