Transistor circuits including fringeless transistors and method of making the same
A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.
1. A semiconductor structure, comprising:
a first field effect transistor comprising a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric;
a second field effect transistor comprising a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric; and
a trench isolation region surrounding the first and the second active regions;
wherein:
the first field effect transistor includes a fringe region in which the first gate electrode extends past the active region in a second horizontal direction which is perpendicular to a first horizontal source region to drain region direction;
the second field effect transistor does not include the fringe region in which the second gate electrode extends past the active region in the second horizontal direction; and
the second field effect transistor is located in a sense amplifier circuit of a driver circuit of a memory device and the first transistor is located outside the sense amplifier circuit of the driver circuit of the memory device.
2. A semiconductor structure, comprising:
a first field effect transistor comprising a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric;
a second field effect transistor comprising a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric; and
a trench isolation region surrounding the first and the second active regions;
wherein;
the first field effect transistor includes a fringe region in which the first gate electrode extends past the active region in a second horizontal direction which is perpendicular to a first horizontal source region to drain region direction;
the second field effect transistor does not include the fringe region in which the second gate electrode extends past the active region in the second horizontal direction; and
the first gate electrode length is narrower than the second gate electrode length along the first horizontal direction.
3. A semiconductor structure, comprising:
a first field effect transistor comprising a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric;
a second field effect transistor comprising a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric; and
a trench isolation region surrounding the first and the second active regions;
wherein:
the first field effect transistor includes a fringe region in which the first gate electrode extends past the active region in a second horizontal direction which is perpendicular to a first horizontal source region to drain region direction;
the second field effect transistor does not include the fringe region in which the second gate electrode extends past the active region in the second horizontal direction;
the trench isolation region comprises a trench isolation structure having a first opening therethrough;
the trench isolation structure comprises a gap region having a recessed horizontal surface, laterally surrounding the first opening, and laterally surrounded by a field region of the trench isolation structure including a topmost surface of the trench isolation structure;
the first active region is located within the first opening through the trench isolation structure;
the first gate electrode comprises a lower gate electrode portion contacting a top surface of the first gate dielectric and a pair of sidewall segments of the trench isolation structure, and comprises an upper gate electrode portion contacting first segments of the recessed horizontal surface of the trench isolation structure; and
a first dielectric gate spacer laterally surrounds the first gate electrode and contacts second segments of the recessed horizontal surface of the trench isolation structure.
4. The semiconductor structure of claim 3 , wherein:
a top surface of the first active region has an active region length along the first horizontal direction and has an active region width along the second horizontal direction;
the lower gate electrode portion has a lower electrode width along the second horizontal direction that is the same as the active region width; and
the upper gate electrode portion has an upper electrode width along the second horizontal direction that is greater than the active region width.
5. The semiconductor structure of claim 3 , further comprising a dielectric isolation spacer contacting sidewalls of the trench isolation structure that connect the recessed horizontal surface of the trench isolation structure to the topmost surface of the trench isolation structure.
6. The semiconductor structure of claim 5 , wherein:
the dielectric isolation spacer comprises a same set of materials as the dielectric gate spacer;
a lateral dimension between an inner periphery of a bottom surface of the dielectric isolation spacer and an outer periphery of the bottom surface of the dielectric isolation spacer is the same as a lateral dimension between an inner periphery of a bottom surface of the dielectric gate spacer and an outer periphery of the bottom surface of the dielectric gate spacer;
the dielectric isolation spacer is not in direct contact with the semiconductor substrate; and
an entirety of the dielectric isolation spacer is located above a horizontal plane including the recessed horizontal surface of the trench isolation structure.
7. The semiconductor structure of claim 3 , wherein:
the first dielectric gate spacer comprises a pair of first bottom surfaces contacting segments of a top surface of the first active region, and a pair of second bottom surfaces contacting the second segments of the recessed horizontal surface of the trench isolation structure and located above a horizontal plane including the pair of first bottom surfaces; and
the first dielectric gate spacer is laterally spaced from sidewalls of the trench isolation structure that connect the recessed horizontal surface of the trench isolation structure to the topmost surface of the trench isolation structure.
8. The semiconductor structure of claim 3 , further comprising a first gate metal-semiconductor alloy portion having a bottom surface that contacts a top surface of the first gate electrode within a horizontal plane located below a horizontal plane including the topmost surface of the trench isolation structure, and having a top surface located above the horizontal plane including the topmost surface of the trench isolation structure.
9. The semiconductor structure of claim 3 , further comprising:
a planarization dielectric layer overlying the first gate electrode; and
a gate contact via structure vertically extending through the planarization dielectric layer and contacting the first gate stack structure and electrically connected to the first gate electrode, wherein the gate contact via structure is located entirely outside an area of a top surface of the first active region in a plan view.
10. The semiconductor structure of claim 9 , wherein the gate contact via structure is located entirely inside an area of the recessed horizontal surface of the trench isolation structure in the plan view.
11. The semiconductor structure of claim 3 , wherein:
the second active region is located within a second opening through the trench isolation structure; and
the second gate electrode comprises a top surface located within a same horizontal plane as a top surface of the first gate electrode and comprises a pair of sidewalls vertically extending straight from a respective edge of the top surface of the second gate electrode to a respective edge of a top surface of a second gate dielectric.
12. The semiconductor structure of claim 11 , wherein an entirety of the pair of sidewalls of the second gate electrode is in contact with a respective sidewall of the trench isolation structure.