Structure having different gate dielectric widths in different regions of substrate
A structure and method of forming different high dielectric constant (high-K) gate dielectrics for different transistors on the same substrate, are disclosed. A first region includes a first transistor(s) on the substrate having a first gate structure having a first gate body over a first high-K gate dielectric. The first gate body and the first high-K gate dielectric have different widths defining a first width difference. A second region includes a second transistor(s) on the substrate having a second gate structure having a second gate body over a second high-K gate dielectric. The second gate body and the second high-K gate dielectric have different widths defining a second width difference. The first width difference is different than the second width difference, i.e., amongst transistors in the different regions. The different gate dielectric widths improve control of overlap capacitance of the transistors without increasing dopants or an annealing temperature.
1. A structure, comprising:
a substrate;
a first region including at least one first transistor on the substrate, the at least one first transistor having a first gate structure having a first gate body over a first high dielectric constant (high-K) gate dielectric, wherein the first gate body has a first body width and the first high-K gate dielectric has a first dielectric width extending horizontally beyond the first gate body, the different widths defining a first width difference;
a second region including at least one second transistor on the substrate, the at least one second transistor having a second gate structure having a second gate body over a second high-K gate dielectric, wherein the second gate body has a second body width and the second high-K gate dielectric has a second dielectric width extending horizontally beyond the second gate body, the different widths defining a second width difference; and
a third region including at least one third transistor on the substrate, the at least one third transistor having a third gate structure having a third gate body over a third high-K gate dielectric, wherein the third gate body has a third body width and the third high-K gate dielectric has a third dielectric width extending horizontally beyond the third gate body, the different widths defining a third width difference,
wherein the first width difference, the second width difference and the third width difference are all different and the first body width, the second body width and each third body width are the same.
2. The structure of claim 1 , further comprising an oxide gate dielectric between each high-K gate dielectric and the substrate.
3. The structure of claim 1 , wherein the first gate body and the second gate body each include a first spacer layer surrounding a sidewall of the respective gate body and a second spacer layer surrounding a sidewall of the first spacer layer, and wherein the first gate body of the first gate structure includes the first spacer layer over an upper surface thereof.
4. The structure of claim 1 , wherein the at least one first transistor includes an input/output transistor and the at least one second transistor includes a logic transistor.
5. A structure, comprising:
a substrate; and
three or more regions on the substrate, each region including at least one transistor on the substrate, every transistor in each of the three or more regions having a gate structure having a gate body over a high dielectric constant (high-K) gate dielectric, wherein the gate body has a body width and the high-K gate dielectric has a dielectric width extending horizontally beyond the gate body, a width offset between the body width and the dielectric width defining a width difference, and
wherein the width difference is different for the respective at least one transistor in each region of the three or more plurality of regions and each body width in the three or more regions are the same.
6. The structure of claim 5 , further comprising an oxide gate dielectric between each high-K gate dielectric and the substrate.
7. The structure of claim 5 , wherein a first gate structure in a first region and a second gate structure in a second region each include a gate body over a respective high-K dielectric, each gate body having a first spacer layer surrounding a sidewall of the gate body and a second spacer layer surrounding a sidewall of the first spacer layer.
8. The structure of claim 5 , wherein at least one transistor in one region of the plurality of regions includes an input/output transistor and at least one transistor in another region of the plurality of regions includes a logic transistor.
9. A method, comprising:
forming at least one first gate structure in a first region of a substrate, each first gate structure having a first gate body over a first high dielectric constant (high-K) gate dielectric, wherein the first gate body has a first body width and the first high-K gate dielectric has a first dielectric width extending horizontally beyond the first gate body, the different widths defining a first width difference;
forming at least one second gate structure in a second region of the substrate, each second gate structure having a second gate body over a second high-K gate dielectric, wherein the second gate body has a second body width and the second high-K gate dielectric has a second dielectric width extending horizontally beyond the second gate body, the different widths defining a second width difference; and
forming at least one third gate structure in at least one third region on the substrate, each third gate structure in a respective third region having a third gate body over a third high-K gate dielectric, wherein the third gate body has a third body width and the third high-K gate dielectric has a third dielectric width extending horizontally beyond the third gate body, the different widths defining a third width difference,
wherein the first width difference, the second width difference and the third width difference are all different and the first body width, the second body width and each third body width are the same.
10. The method of claim 9 , wherein forming the at least one first gate structure and the at least one second gate structure includes:
forming the at least one first gate structure in the first region and the second region of the substrate;
covering the at least one first gate structure in the first region, leaving the at least one first gate structure exposed in the second region;
etching to trim a portion of the first high-K gate dielectric from each first gate structure in the second region, forming the at least one second gate structure in the second region; and
removing the covering.
11. The method of claim 9 , further comprising forming an oxide gate dielectric between each high-K gate dielectric and the substrate.
12. The method of claim 9 , wherein forming the at least one first gate structure and the at least one second gate structure includes:
forming the at least one first gate structure in a plurality of regions of the substrate including a first region and a second region;
forming a first spacer layer surrounding a sidewall of each first gate structure in all of the plurality of regions of the substrate;
covering the at least one first gate structure in the first region, leaving the at least one first gate structure exposed in the second region;
etching to remove the first spacer layer from at least the first high-K dielectric of each first gate structure in the second region;
etching to trim a portion of the first high-K gate dielectric from each first gate structure in the second region, forming the at least one second gate structure in the second region; and
removing the covering.
13. The method of claim 12 , further comprising forming a second spacer layer over the at first spacer layer.
14. The method of claim 13 , wherein etching to remove the first spacer layer removes the first spacer layer from an upper surface of the second gate body of the at least one second gate structure.