High electron mobility transistor with source and drain electrodes below the channel
A superconductor transistor structure includes a source electrode and a drain electrode on a same plane as the source electrode. There is a channel region on top of the source and drain electrodes and configured to carry a current. A gate structure comprising a metallic material is on top of the channel region. The source and drain are located on a side that is opposite to that of the gate structure, with respect to the channel region.
1. A semiconductor transistor structure, comprising:
a source electrode;
a drain electrode on a same plane as the source electrode;
a channel region on top of the source and drain electrodes and configured to carry a current; and
a gate structure comprising a metallic material on top of the channel region, wherein:
the source and drain electrodes are located on a side that is opposite to that of the gate structure, with respect to the channel region; and
the gate structure is T shaped.
2. The semiconductor transistor structure of claim 1 , wherein the channel region comprises indium gallium arsenide (InGaAs).
3. The semiconductor transistor structure of claim 1 , wherein the semiconductor transistor structure is a high-electron-mobility transistor (HEMT) and part of a low noise amplifier configured to operate in a cryogenic environment.
4. A semiconductor transistor structure, comprising:
a source electrode;
a drain electrode on a same plane as the source electrode;
a channel region on top of the source and drain electrodes and configured to carry a current;
a gate structure comprising a metallic material on top of the channel region;
a substrate configured as a chip carrier; and
an oxide layer on top of the chip carrier substrate, wherein:
the source and drain electrodes are located on a side that is opposite to that of the gate structure, with respect to the channel region;
the source and drain electrodes are on top of the chip carrier substrate; and
the source and drain electrodes are on a left and a right side of the oxide layer, respectively.
5. The semiconductor transistor structure of claim 4 , further comprising:
a first N+ contact on top of the source electrode; and
a second N+ contact on top of the drain electrode.
6. The semiconductor transistor structure of claim 4 , further comprising a first buffer layer on top of the oxide and source and drain contacts and below the channel region.
7. The semiconductor transistor structure of claim 6 , wherein the first buffer layer comprises indium phosphide (InP).
8. The semiconductor transistor structure of claim 6 , further comprising:
a gate barrier on top of the channel region; and
a second buffer layer on top of the gate barrier and below the gate structure.
9. The semiconductor transistor structure of claim 8 , wherein the gate barrier comprises indium aluminum arsenide (InAlAs).
10. The semiconductor transistor structure of claim 8 , wherein the second buffer layer comprises indium phosphide (InP).
11. A method of fabricating a semiconductor transistor structure, comprising:
providing a first substrate;
providing a first buffer layer on top of the first substrate;
providing a gate barrier layer on top of the first buffer layer;
providing a quantum well channel layer on top of the gate barrier layer;
providing a second buffer layer on top of the quantum well channel layer;
providing a contact layer on top of the second buffer layer;
providing a first photoresist layer having a pattern, on top of the contact layer, to define an etch gate recess region;
removing a center portion of the contact layer below the photoresist pattern, thereby defining a source and a drain on the contact layer;
removing the first photoresist;
depositing an electrode on the drain contact and an electrode on the source contact;
depositing an oxide layer on top of the source and drain electrodes, and the buffer layer;
planarizing the oxide layer;
flipping the transistor structure and direct bonding to a carrier substrate;
removing the first substrate, thereby exposing the first buffer layer;
providing a second photoresist layer having a pattern on top of the exposed first buffer layer;
depositing a metal gate structure on top of the exposed first buffer layer; and
configuring the gate structure to have a T shape.
12. The method of claim 11 , wherein the quantum well channel comprises indium gallium arsenide (InGaAs).
13. The method of claim 11 , wherein alignment markers are used for the deposition of the electrodes on the drain and source contacts.
14. The method of claim 11 , wherein the direct bonding to the carrier substrate comprises:
covering at least one of a surface of the oxide layer or the carrier substrate with a layer of adhesive oxide;
aligning the flipped semiconductor structure with the carrier substrate;
bonding the flipped semiconductor structure with the carrier substrate to create a combined structure; and
annealing the combined structure to create a covalent bond between the oxide layer and the carrier substrate.
15. The method of claim 11 , wherein the quantum well channel layer comprises indium gallium arsenide (InGaAs).
16. The method of claim 11 , wherein the first buffer layer comprises indium phosphide (InP).
17. The method of claim 11 , wherein the gate barrier layer comprises indium aluminum arsenide (InAlAs).
18. The method of claim 11 , wherein the second buffer layer comprises indium phosphide (InP).