IP Library Granted Patent US 12,200,862
Granted Patent B1
US 12,200,862 · App. 17/698,139 · Granted Jan 14, 2025

Panel molded electronic assemblies with integral terminals

Inventors: Patrizio Vinciarelli (Boston, MA); Michael B. LaFleur (East Hampstead, NH)
Assignee: Vicor Corporation
H05K1/113H05K1/116H05K1/181H05K1/184H05K3/243H05K3/3405H05K3/429
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Quick Facts
Patent No.
US 12,200,862
App. No.
17/698,139
Granted
Jan 14, 2025
Kind
B1
Abstract

Encapsulated electronic modules having complex contact structures may be formed by encapsulating panels containing a substrate comprising pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within terminal holes and other holes drilled in the panel within the boundaries of the cut lines. Slots may be cut in the panel along the cut lines. The interior of the holes, as well as surfaces within the slots and on the surfaces of the panel may be metallized, e.g. by a series of processes including plating. Terminals may be inserted into the terminal holes and connected to conductive features or plating within the holes. A conductive element may be provided on the substrate to connect to a terminal. Alternatively solder may be dispensed into the holes for surface mounting.

Claims (74)

1. Apparatus comprising:

an over-molded electronic module including:

a multilayer printed circuit board (“PCB”) having alternating electrically conductive layers and insulating layers in a thickness direction, a first plurality of electronic components mounted to a first surface of the PCB;

a first layer of cured encapsulant covering the first plurality of components and the first surface of the PCB, the first layer of cured encapsulant forming a first exterior module surface, wherein the cured encapsulant is composed of cured molding compound, the molding compound prior to being cured is suitable to being injected into a mold that defines an upper surface contour of the first layer of cured encapsulant, and the cured encapsulant is composed of a material different from the insulating layers of the PCB;

one or more conductive features buried beneath the first exterior module surface;

one or more terminal holes formed in the first layer of cured encapsulant, each terminal hole intersecting a respective set of the conductive features to expose respective portions of the selected set of the conductive features; and

one or more conductive terminals, wherein each conductive terminal has a first portion that extends beyond the first exterior module surface and a second portion disposed within the terminal hole and electrically connected to the respective portions of the respective set of conductive features;

wherein each respective conductive terminal is electrically connected to the respective portions of the one or more conductive features exposed within the respective terminal holes and forms a pressure fit with conductive features in the respective terminal holes.

2. The apparatus of claim 1 , further comprising a conductive metal layer formed on an interior surface of selected terminal holes in contact with the respective portions of the respective set of conductive features within the respective terminal hole and the pressure fit is with the conductive metal layer.

3. The apparatus of claim 2 wherein the selected set of conductive features comprises one or more of the conductive layers of the PCB, each selected terminal hole is formed through at least a portion of the PCB, and wherein the respective portions of the one or more conductive features include edges of the one or more conductive layers.

4. The apparatus of claim 2 , further comprising a conductive metal pad formed on the first exterior module surface surrounding one or more of the selected terminal holes, the metal pad being continuous with the conductive metal layer on the interior surface of the one or more of the selected terminal holes and providing an electrical contact on the first exterior module surface connected to the one or more exposed features within the respective terminal hole.

5. The apparatus of claim 4 , further comprising a solder connection between a portion of the conductive terminal and the conductive metal layer on the interior surface of the one or more selected terminal holes.

6. The apparatus of claim 4 , further comprising a solder connection between a portion of the conductive terminal and the conductive metal pad.

7. The apparatus of claim 1 , further comprising:

one or more mounting holes formed in the first layer of cured encapsulant, each mounting hole intersecting a respective second set of the conductive features to expose respective portions of the respective second set of conductive features in the respective mounting hole;

each mounting hole having a conductive metal layer formed on an interior surface of the respective mounting hole in contact with the exposed respective portions of the respective second set of conductive features within the respective mounting hole and a conductive metal mounting pad formed on the exterior module surface surrounding the respective mounting hole, the metal mounting pad being continuous with the conductive metal layer on the interior surface of the respective mounting hole and providing an electrical contact on the exterior module surface connected to the exposed respective portions of the respective second set of the conductive features.

8. The apparatus of claim 7 wherein the metal mounting pad further comprises a conductive metal shield covering at least 25 percent of the exterior module surface.

9. The apparatus of claim 8 wherein the conductive shield covers at least 50 percent of the exterior module surface and connects a plurality of the mounting holes.

10. The apparatus of claim 7 wherein the mounting holes extend completely through the electronic module.

11. The apparatus of claim 1 wherein the electronic module further comprises a second set of electronic components mounted to a second surface of the PCB, and a second layer of cured encapsulant covers the second set of components and the second surface of the PCB, the second layer of cured encapsulant forming a second exterior module surface.

12. The apparatus of claim 11 , further comprising a conductive metal layer formed on an interior surface of each of selected terminal holes in contact with the respective portions of the respective set of conductive features within the respective terminal hole.

13. The apparatus of claim 12 wherein the selected set of conductive features comprises one or more of the conductive layers of the PCB, each selected terminal hole is formed through at least a portion of the PCB, and wherein the respective portions of the one or more conductive features include edges of the one or more conductive layers.

14. The apparatus of claim 12 , further comprising a conductive metal pad formed on the first exterior module surface surrounding one or more of the selected terminal holes, the metal pad being continuous with the conductive metal layer on the interior surface of the one or more of the selected terminal holes and providing an electrical contact on the first exterior module surface connected to the one or more exposed features within the respective terminal hole.

15. The apparatus of claim 14 , further comprising a solder connection between a portion of the conductive terminal and the conductive metal layer on the interior surface of the one or more selected terminal holes.

16. The apparatus of claim 14 , further comprising a solder connection between a portion of the conductive terminal and the conductive metal pad.

17. The apparatus of claim 11 , further comprising:

one or more mounting holes formed in the first and second layers of cured encapsulant and PCB, each mounting hole extending completely through the module and intersecting a respective second set of the conductive features to expose respective portions of the respective second set of conductive features in the respective mounting hole;

each mounting hole having a conductive metal layer formed on an interior surface of the respective mounting hole in contact with the exposed respective portions of the respective second set of conductive features within the respective mounting hole and a conductive metal mounting pad formed on one or both of the first and second exterior module surfaces surrounding the respective mounting hole, the metal mounting pad being continuous with the conductive metal layer on the interior surface of the respective mounting hole and providing an electrical contact on the exterior module surface connected to the exposed respective portions of the respective second set of the conductive features.

18. The apparatus of claim 7 wherein the metal mounting pad further comprises a conductive metal shield covering at least 25 percent of one or both of the first and second exterior module surfaces.

19. The apparatus of claim 18 wherein the conductive shield covers at least 50 percent of both of the first and second exterior module surfaces and electrically connects to a plurality of the mounting holes.

20. The apparatus of claim 2 wherein the selected set of conductive features comprises a conductive trace on a surface of the PCB, each selected terminal hole is limited in depth to the surface of the PCB, and wherein the respective portions of the one or more conductive features include a surface of the conductive trace at a bottom of each terminal hole.

21. The apparatus of claim 1 wherein the one or more terminal holes comprise one or more blind holes, and each blind hole extends partially into, but not completely through, the electronic module.

22. The apparatus of claim 11 , wherein each respective conductive terminal comprises a columnar portion extending beyond the first exterior surface of the electronic module and being adapted to engage with a through hole in a second printed circuit board external to the electronic module.

23. The apparatus of claim 11 wherein each respective conductive terminal comprises a threaded hole adapted to accept a threaded fastener.

24. The apparatus of claim 11 wherein each of at least some of the one or more conductive terminals includes a portion lying within the respective terminal hole and configured to provide one or more gaps between the portion of the conductive terminal and a sidewall surface of the terminal hole;

wherein at least one of

(i) the portion of each conductive terminal lying within the respective terminal hole includes one or more indentations to provide the one or more gaps between the portion of the conductive terminal and the sidewall surface of the terminal hole,

(ii) each of one or more of the terminal holes has a curved sidewall surface, and the portion of the respective conductive terminal lying within the terminal hole includes one or more flat surfaces to provide the one or more gaps between the one or more flat surfaces of the portion of the conductive terminal and the curved sidewall surface of the terminal hole,

(iii) each of one or more of the terminal holes has a circular sidewall, and the portion of the respective conductive terminal lying within the terminal hole has an approximately octagonal shape to provide the gaps between the portion of the conductive terminal and the curved sidewall surface of the terminal hole, or

(iv) each of one or more of the terminal holes has a non-circular sidewall, and the portion of the respective conductive terminal lying within the terminal hole has a circular shape to provide the one or more gaps between the non-circular sidewall surface of the terminal hole and the portion of the respective conductive terminal lying within the terminal hole.

25. The apparatus of claim 24 wherein the portion of each conductive terminal lying within the respective terminal hole includes one or more indentations to provide the one or more gaps between the portion of the conductive terminal and the sidewall surface of the terminal hole.

26. The apparatus of claim 24 wherein each of one or more of the terminal holes has a curved sidewall surface, and the portion of the respective conductive terminal lying within the terminal hole includes one or more flat surfaces to provide the one or more gaps between the one or more flat surfaces of the portion of the conductive terminal and the curved sidewall surface of the terminal hole.

27. The apparatus of claim 24 , comprising, for each of one or more of the terminal holes, solder that fills a region between the sidewall surface of the terminal hole and the exterior surface of the respective conductive terminal,

wherein the one or more gaps are adapted to allow gases to escape from the respective terminal hole during soldering.

28. The apparatus of claim 24 wherein each of one or more of the terminal holes has a circular sidewall, and the portion of the respective conductive terminal lying within the terminal hole has an approximately octagonal shape to provide the gaps between the portion of the conductive terminal and the curved sidewall surface of the terminal hole.

29. The apparatus of claim 24 wherein each of one or more of the terminal holes has a circular cross-section, and the portion of the respective conductive terminal lying within the circular terminal hole has one or more indentations providing one or more gaps between the portion of the conductive terminal and the sidewall surface of the circular terminal hole.

30. The apparatus of claim 24 wherein each of one or more of the terminal holes has a non-circular sidewall, and the portion of the respective conductive terminal lying within the terminal hole has a circular shape to provide the one or more gaps between the non-circular sidewall surface of the terminal hole and the portion of the respective conductive terminal lying within the terminal hole.

31. The apparatus of claim 11 wherein the electronic module comprises:

one or more second conductive features embedded in the first layer of cured encapsulant; wherein each of the one or more terminal holes formed in the first layer of cured encapsulant intersects a respective set of the second conductive features to expose respective portions of the set of the second conductive features, and the respective conductive terminal within the terminal hole is electrically connected to the respective portions of the respective set of second conductive features.

32. The apparatus of claim 31 wherein the one or more first conductive features are made of a malleable electrically conductive material.

33. The apparatus of claim 32 wherein the one or more first conductive features are made of copper.

34. The apparatus of claim 31 wherein the first conductive feature at each terminal hole is electrically connected to a respective conductive trace or pad on the printed circuit board.

35. The apparatus of claim 31 wherein each terminal hole has an upper portion that has a larger diameter and a lower portion that has a smaller diameter.

36. The apparatus of claim 31 wherein each conductive terminal has an upper portion that has a smaller diameter and a lower portion that has a larger diameter.

37. The apparatus of claim 11 wherein each terminal hole has an upper portion that has a larger diameter and a lower portion that has a smaller diameter.

38. The apparatus of claim 11 wherein each conductive terminal has an upper flange that has a first diameter larger than a diameter of the respective terminal hole, and a lower portion that has a second diameter that is smaller than the first diameter;

wherein the upper flange is positioned above a surface of the first layer of cured encapsulant.

39. The apparatus of claim 38 wherein each terminal hole has an upper portion that has a larger diameter and a lower portion that has a smaller diameter.

40. The apparatus of claim 38 wherein each conductive terminal has an upper portion that has a smaller diameter and a lower portion that has a larger diameter.

41. The apparatus of claim 17 wherein the one or more terminal holes comprise one or more blind holes, and each blind hole extends partially into, but not completely through, the electronic module.

42. The apparatus of claim 1 , wherein the cured encapsulant comprises cured molding compound.

43. The apparatus of claim 1 , wherein the cured encapsulant comprises a thermally conductive epoxy.

44. The apparatus of claim 1 , wherein the insulating layers of the PCB comprise at least one of impregnated fiberglass or ceramic.

45. The apparatus of claim 1 , wherein the printed circuit board comprises one or more conductive traces disposed on a top surface of the printed circuit board,

one or more of the terminal holes pass through the first layer of cured encapsulant to reach the one or more conductive traces, and

one or more of the conductive terminals contact the one or more conductive traces.

46. The apparatus of claim 1 , wherein the electronic module comprises one or more conductive pucks mounted on a top surface of the printed circuit board,

one or more of the terminal holes pass through the first layer of cured encapsulant to reach the one or more conductive pucks, and

one or more of the conductive terminals contact the one or more conductive traces.

47. The apparatus of claim 1 , wherein the one or more terminal holes extend from the first exterior module surface to a top surface of the printed circuit board and do not pass through any portion of the printed circuit board.

48. The apparatus of claim 1 , wherein the pressure fit comprises a frictional compressive fit configured to mechanically secure the conductive terminal within the respective terminal hole.

49. The apparatus of claim 48 , wherein the electronic module comprises:

a conductive metal layer formed on an interior surface of selected terminal holes in contact with the respective portions of the respective set of conductive features within the respective terminal hole and the pressure fit is with the conductive metal layer; and

a solder connection between a portion of the conductive terminal and the conductive metal layer on the interior surface of the one or more selected terminal holes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2022
From: VINCIARELLI, PATRIZIO; LAFLEUR, MICHAEL B.
To: VLT, INC.
Reel/Frame 059969/0637 →
MERGER AND CHANGE OF NAME Recorded May 12, 2022
From: VLT, INC.; VICOR CORPORATION
To: VICOR CORPORATION
Reel/Frame 059969/0665 →
Continuity (2)
Division 17026567 · Sep 21, 2020
Division 16218395 · Dec 12, 2018
References Cited (211)
US 3846741A · Kunkle et al. · 1974 [cited by applicant]
US 4211603A · Reed · 1980 [cited by applicant]
US 4223970A · Walter · 1980 [cited by applicant]
US 4230385A · Ammon et al. · 1980 [cited by applicant]
US 4394711A · Conley · 1983 [cited by applicant]
US 4526429A · Kirkman · 1985 [cited by applicant]
US RE32212E · Walter et al. · 1986 [cited by applicant]
US 4711026A · Swiggett · 1987 [cited by examiner]
US 4742477A · Phillips et al. · 1988 [cited by applicant]
US 4859807A · Swiggett · 1989 [cited by examiner]
US 4917526A · Paterson · 1990 [cited by applicant]
US 5168432A · Murphy et al. · 1992 [cited by applicant]
US 5206795A · Belanger, Jr. · 1993 [cited by applicant]
US 5247423A · Lin et al. · 1993 [cited by applicant]
US 5321351A · Swart et al. · 1994 [cited by applicant]
US 5408189A · Swart et al. · 1995 [cited by applicant]
US 5438294A · Smith · 1995 [cited by applicant]
US 5728600A · Vinciarelli et al. · 1998 [cited by applicant]
US 5973923A · Jitaru et al. · 1999 [cited by applicant]
US RE36442E · Kardos · 1999 [cited by applicant]
US 6001671A · Fjelstad · 1999 [cited by applicant]
US 6028354A · Hoffman · 2000 [cited by applicant]
US 6031253A · Kobayashi · 2000 [cited by applicant]
US 6031743A · Carpenter et al. · 2000 [cited by applicant]
US 6035261A · Carpenter et al. · 2000 [cited by applicant]
US 6110213A · Vinciarelli et al. · 2000 [cited by applicant]
US 6116916A · Kasai · 2000 [cited by applicant]
US 6118186A · Scott et al. · 2000 [cited by applicant]
US 6230403B1 · Skoolicas et al. · 2001 [cited by applicant]
US 6262600B1 · Haigh et al. · 2001 [cited by applicant]
US 6275958B1 · Carpenter et al. · 2001 [cited by applicant]
US 6288905B1 · Chung · 2001 [cited by examiner]
US 6300749B1 · Castelli et al. · 2001 [cited by applicant]
US 6311279B1 · Nguyen · 2001 [cited by applicant]
US 6403009B1 · Saxelby, Jr. et al. · 2002 [cited by applicant]
US 6421262B1 · Saxelby et al. · 2002 [cited by applicant]
US 6466458B2 · Zhang et al. · 2002 [cited by applicant]
US 6566234B1 · Capote · 2003 [cited by examiner]
US 6586822B1 · Vu · 2003 [cited by applicant]
US 6603292B1 · Schouten et al. · 2003 [cited by applicant]
US 6646886B1 · Popovich et al. · 2003 [cited by applicant]
US 6700361B2 · Gregorius · 2004 [cited by applicant]
US 6788033B2 · Vinciarelli · 2004 [cited by applicant]
US 6847853B1 · Vinciarelli et al. · 2005 [cited by applicant]
US 6911848B2 · Vinciarelli · 2005 [cited by applicant]
US 6930893B2 · Vinciarelli · 2005 [cited by applicant]
US 6934166B2 · Vinciarelli · 2005 [cited by applicant]
US 6969909B2 · Briere · 2005 [cited by applicant]
US 6975098B2 · Vinciarelli · 2005 [cited by applicant]
US 6982876B1 · Young · 2006 [cited by applicant]
US 6984965B2 · Vinciarelli · 2006 [cited by applicant]
US 6985341B2 · Vinciarelli et al. · 2006 [cited by applicant]
US 7015587B1 · Poddar · 2006 [cited by applicant]
US 7030469B2 · Mahadevan et al. · 2006 [cited by applicant]
US 7145786B2 · Vinciarelli · 2006 [cited by applicant]
US 7187263B2 · Vinciarelli et al. · 2007 [cited by applicant]
US 7190057B2 · Seki · 2007 [cited by applicant]
US 7198987B1 · Warren et al. · 2007 [cited by applicant]
US 7268425B2 · Mallik · 2007 [cited by applicant]
US 7294007B1 · Lawlyes · 2007 [cited by applicant]
US RE40072E · Prager et al. · 2008 [cited by applicant]
US 7361844B2 · Vinciarelli et al. · 2008 [cited by applicant]
US 7474185B2 · Hooey et al. · 2009 [cited by applicant]
US 7494843B1 · Lin et al. · 2009 [cited by applicant]
US 7561446B1 · Vinciarelli · 2009 [cited by applicant]
US 7646610B2 · Watanabe · 2010 [cited by applicant]
US 7745259B2 · Sasaki et al. · 2010 [cited by applicant]
US 7772036B2 · Bauer et al. · 2010 [cited by applicant]
US 7786837B2 · Hebert · 2010 [cited by applicant]
US 8030750B2 · Kim et al. · 2011 [cited by applicant]
US 8138584B2 · Wang · 2012 [cited by applicant]
US 8232783B2 · Yanagawa · 2012 [cited by applicant]
US 8263434B2 · Pagaila · 2012 [cited by applicant]
US 8288846B2 · Narendra et al. · 2012 [cited by applicant]
US 8427269B1 · Vinciarelli et al. · 2013 [cited by applicant]
US 8461672B2 · Haba et al. · 2013 [cited by applicant]
US 8488324B2 · Becker et al. · 2013 [cited by applicant]
US 8513789B2 · Haba et al. · 2013 [cited by applicant]
US 8551815B2 · Avsian et al. · 2013 [cited by applicant]
US 8582333B2 · Oraw et al. · 2013 [cited by applicant]
US 8629543B2 · McElrea et al. · 2014 [cited by applicant]
US 8966747B2 · Vinciarelli et al. · 2015 [cited by applicant]
US 9105613B1 · Chen · 2015 [cited by examiner]
US 9107290B1 · Chen · 2015 [cited by examiner]
US 9112422B1 · Vinciarelli · 2015 [cited by applicant]
US 9166481B1 · Vinciarelli et al. · 2015 [cited by applicant]
US 9305862B2 · McElrea et al. · 2016 [cited by applicant]
US 9402319B2 · Vinciarelli et al. · 2016 [cited by applicant]
US 9516761B2 · Vinciarelli et al. · 2016 [cited by applicant]
US 9819263B2 · Zeng et al. · 2017 [cited by applicant]
US 9936580B1 · Vinciarelli et al. · 2018 [cited by applicant]
US 10014798B1 · Vinciarelli et al. · 2018 [cited by applicant]
US 10020752B1 · Vinciarelli et al. · 2018 [cited by applicant]
US 10158357B1 · Vinciarelli et al. · 2018 [cited by applicant]
US 10231333B1 · Liu et al. · 2019 [cited by applicant]
US 10264664B1 · Vinciarelli et al. · 2019 [cited by applicant]
US 10277105B1 · Vinciarelli et al. · 2019 [cited by applicant]
US 10390437B2 · Kudou et al. · 2019 [cited by applicant]
US 10506712B1 · Tsao · 2019 [cited by examiner]
US 10512182B2 · Suzuki · 2019 [cited by applicant]
US 10681821B2 · Karpman · 2020 [cited by applicant]
US 10877534B2 · Zeng · 2020 [cited by applicant]
US 11324107B1 · Vinciarelli et al. · 2022 [cited by applicant]
US 11336167B1 · Vinciarelli et al. · 2022 [cited by applicant]
US 11398770B1 · Vinciarelli · 2022 [cited by applicant]
US 20010018285A1 · Mizumura · 2001 [cited by applicant]
US 20010018286A1 · Mizumura · 2001 [cited by applicant]
US 20010023980A1 · Ohmori · 2001 [cited by applicant]
US 20010032388A1 · Morris · 2001 [cited by applicant]
US 20030087538A1 · Ueno · 2003 [cited by applicant]
US 20030162434A1 · Kamiya · 2003 [cited by applicant]
US 20030168499A1 · Tanabe et al. · 2003 [cited by applicant]
US 20040100778A1 · Vinciarelli · 2004 [cited by examiner]
US 20040207089A1 · Masuda · 2004 [cited by applicant]
US 20040251554A1 · Masuda · 2004 [cited by applicant]
US 20050048692A1 · Hanada et al. · 2005 [cited by applicant]
US 20050168960A1 · Asahi et al. · 2005 [cited by applicant]
US 20060011383A1 · Noguchi · 2006 [cited by examiner]
US 20060127652A1 · Kanaya et al. · 2006 [cited by applicant]
US 20060180346A1 · Knight et al. · 2006 [cited by applicant]
US 20060216867A1 · Kawata · 2006 [cited by examiner]
US 20060272150A1 · Eguchi et al. · 2006 [cited by applicant]
US 20060283547A1 · Yuri · 2006 [cited by examiner]
US 20060283625A1 · Yamamichi · 2006 [cited by examiner]
US 20070102142A1 · Reis et al. · 2007 [cited by applicant]
US 20070241440A1 · Hoang et al. · 2007 [cited by applicant]
US 20080000680A1 · Cho et al. · 2008 [cited by applicant]
US 20080078572A1 · Watanabe et al. · 2008 [cited by applicant]
US 20090070996A1 · Sakamoto et al. · 2009 [cited by applicant]
US 20090160065A1 · Haba et al. · 2009 [cited by applicant]
US 20100013085A1 · Oi · 2010 [cited by examiner]
US 20100149768A1 · Takaike · 2010 [cited by examiner]
US 20100170085A1 · Schaaf et al. · 2010 [cited by applicant]
US 20100290199A1 · Schmid · 2010 [cited by examiner]
US 20100328913A1 · Kugler et al. · 2010 [cited by applicant]
US 20100330725A1 · Yoshizawa et al. · 2010 [cited by applicant]
US 20110088936A1 · Schaaf et al. · 2011 [cited by applicant]
US 20110100691A1 · Yugawa · 2011 [cited by examiner]
US 20110203839A1 · Iwamoto · 2011 [cited by examiner]
US 20110314666A1 · Harazono · 2011 [cited by examiner]
US 20120152600A1 · Nishioka · 2012 [cited by examiner]
US 20120170240A1 · Tanaka · 2012 [cited by applicant]
US 20120199958A1 · Horibe · 2012 [cited by applicant]
US 20130081866A1 · Furutani · 2013 [cited by examiner]
US 20130083495A1 · Moon et al. · 2013 [cited by applicant]
US 20130153279A1 · Hayashi · 2013 [cited by examiner]
US 20130170148A1 · Sun · 2013 [cited by applicant]
US 20140034373A1 · Yoshikawa · 2014 [cited by examiner]
US 20140124906A1 · Park · 2014 [cited by examiner]
US 20140124907A1 · Park · 2014 [cited by examiner]
US 20140355218A1 · Vinciarelli et al. · 2014 [cited by applicant]
US 20150173258A1 · Chen · 2015 [cited by examiner]
US 20160007460A1 · Shimizu · 2016 [cited by examiner]
US 20160014898A1 · Adachi · 2016 [cited by examiner]
US 20160021758A1 · Furutani · 2016 [cited by examiner]
US 20160021759A1 · Furutani · 2016 [cited by examiner]
US 20160042861A1 · Mano · 2016 [cited by examiner]
US 20160043027A1 · Inagaki · 2016 [cited by examiner]
US 20160044780A1 · Inagaki · 2016 [cited by examiner]
US 20160128215A1 · Kanzaki et al. · 2016 [cited by applicant]
US 20160293535A1 · Fukasawa · 2016 [cited by examiner]
US 20160374194A1 · Miki · 2016 [cited by examiner]
US 20170011982A1 · Theuss · 2017 [cited by examiner]
US 20170013748A1 · Saji et al. · 2017 [cited by applicant]
US 20170048981A1 · Hu · 2017 [cited by examiner]
US 20170115144A1 · Watanabe et al. · 2017 [cited by applicant]
US 20170336584A1 · Ariga et al. · 2017 [cited by applicant]
US 20170372991A1 · Tsukamoto · 2017 [cited by examiner]
US 20180042124A1 · Makino · 2018 [cited by examiner]
US 20190059152A1 · Boozer · 2019 [cited by examiner]
US 20190080931A1 · Ito et al. · 2019 [cited by applicant]
US 20190116667A1 · Chen · 2019 [cited by examiner]
EP 2863531 · 2015 [cited by applicant]
JP H02280666 · 1990 [cited by applicant]
JP H04293293 · 1992 [cited by applicant]
WO WO2004017399 · 2004 [cited by applicant]
U.S. Appl. No. 14/731,287, filed Jun. 4, 2015, Vinciarelli et al. [cited by applicant]
U.S. Appl. No. 14/822,561, filed Aug. 10, 2015, Vinciarelli. [cited by applicant]
U.S. Appl. No. 14/874,054, filed Oct. 2, 2015, Vinciarelli. [cited by applicant]
Amendment after Allowance Pursuant to 37 C.F.R. §1.312 in U.S. Appl. No. 13/044,063, dated Mar. 3, 2015, 17 pages. [cited by applicant]
AN2738, Application Note, “L6390 half-bridge gate driver,” STMicroelectronics, Aug. 2009, 54 pages. [cited by applicant]
AND8311/D, “Understanding the LLC Structure in Resonant Applications,” Christophe Basso, ON Semiconductor, Jan. 2008, 16 pages. [cited by applicant]
Brown, “Point of Load Converters—The Topologies, Converters, and Switching Devices Required for Efficient Conversion,” Presented at PCIM Conference, Nuremberg, Germany, May 14-16, 2002, 6 pages. [cited by applicant]
Burton et al., “FIVR—Fully Integrated Voltage Regulators on 4th Generation Intel® Core™M SoCs,” Presented at 2014 IEEE Applied Power Electronics Conference and Exposition—APEC 2014, Fort Worth, TX, USA, Mar. 16-20, 2014… [cited by applicant]
Cao et al., “A Family of Zero Current Switching Switched-Capacitor DCDC converters,” Presented at 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Palm Springs, CA, USA, Feb. 21-… [cited by applicant]
Cao et al., “Zero-Current-Switching Multilevel Modular Switched Capacitor DC-DC Converter” IEEE Transactions on Industry Applications, Sep. 2010, 46(6):2536-2544. [cited by applicant]
Extended European Search Report in European Appln No. 16173089.0, dated Feb. 14, 2017, 8 pages. [cited by applicant]
ISL6210, “Dual Synchronous Rectified MOSFET Drivers,” Intersil Americas Inc., Dec. 9, 2008, 10 pages. [cited by applicant]
Miller, “12V PowerStage in Embedded Die System-in-Package,” Presented at APEC 2015: Applied Power Electronics Conference and Exposition, Charlotte, NC, USA, Mar. 15-19, 2015, 33 pages. [cited by applicant]
Notice of Allowance in U.S. Appl. No. 15/616,288, dated Dec. 11, 2018, 9 pages. [cited by applicant]
Notice of Allowance in U.S. Appl. No. 13/044,063, dated Feb. 20, 2015, 15 pages. [cited by applicant]
Notice of Allowance in U.S. Appl. No. 13/044,063, dated Jun. 5, 2015, 11 pages. [cited by applicant]
Notice of Allowance in U.S. Appl. No. 14/682,187, dated Jan. 17, 2017, 22 pages. [cited by applicant]
Notice of Allowance in U.S. Appl. No. 15/091,346, dated Aug. 13, 2018, 8 pages. [cited by applicant]
Notice of Allowance in U.S. Appl. No. 15/091,346, dated May 21, 2018, 9 pages. [cited by applicant]
Office Action in European Appln. No. 16173089.0, dated Apr. 10, 2017, 2 pages. [cited by applicant]
Office Action in U.S. Appl. No. 13/044,063, dated May 23, 2014, 24 pages. [cited by applicant]
Okudaira et al., “A New Quasi-Resonant Inverter With Two-way Short-circuit Switch Across A Resonant Capacitor,” Presented at Power Conversion Conference, Osaka, Japan, Apr. 2002, 3:1496-1501. [cited by applicant]
Oraw et al., “Load Adaptive, High Efficiency, Switched Capacitor Intermediate Bus Converter,” Presented at IEEE Telecommunications Energy Conference, Rome, Italy, Sep. 30-Oct. 4, 2007, pp. 628-635. [cited by applicant]
psma.com [online], “A 400 Amp Fully Integrated Silicon Voltage Regulator with in-die Magnetically Coupled Embedded Inductors,” Nov. 11, 2013, retrieved on Aug. 3, 2016, retrieved from URL<http://www.psma.com/sites/defau… [cited by applicant]
Reply to Office Action of May 23, 2014 in U.S. Appl. No. 13/044,063, dated Oct. 24, 2014, 39 pages. [cited by applicant]
Seeman et al., “Analysis and optimization of switched-capacitor dc-dc converters,” Power Electronics, IEEE Transactions, Mar. 2008, 23:841-851. [cited by applicant]
TND359, “High-Efficiency 255W ATX Power Supply Reference Design Documentation Package,” ON Semiconductor, Jan. 2009, 37 pages. [cited by applicant]
Supplemental Notice of Allowability in U.S. Appl. No. 13/044,063, dated Apr. 20, 2015, 5 pages. [cited by applicant]
Watson, “New Techniques in the Design of Distributed Power System,” Dissertation, Aug. 7, 1998, 32 pages. [cited by applicant]
Yeung et al., “Generalised analysis of switched-capacitor step-down quasi-resonant converter,” Electronics Letters, Aug. 2002, 38:263-264. [cited by applicant]
Yeung et al., “Zero-current switching switched-capacitor quasiresonant step-down converter,” Electric Power Applications, IEE Proceedings, Mar. 2002, 149(2):111-121. [cited by applicant]
[No Author Listed], “Design Guide & Applications Manual: For VI-200 and VI-J00 Family DC-DC Converters and Configurable Power Supplies,” VICOR Corporation, Dec. 2013, 100 pages. [cited by applicant]
[No Author Listed], “VI Brick® AC Front End Evaluation Board,” VICOR PowerBench, Nov. 2012, 111:1-6. [cited by applicant]
Button et al., “Digital control technologies for modular DC-DC converters,” Presented at the Proceedings of the IEEE Aerospace Conference, Big Sky, Montana, USA, Mar. 25, 2000, 5:355-362. [cited by applicant]
Gerber et al., “High Density Packaging of the Passive Components in an Automotive DC/DC Converter,” IEEE Transactions on Power Electronics, Mar. 2005, 20(2):268-275. [cited by applicant]
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