Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.
1. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
insulator-material bodies in and longitudinally-along opposing sides of individual of the memory blocks in a lowest of the conductive tiers, the insulator-material bodies being spaced relative one another longitudinally-along the memory blocks; and
conductive material in the lowest conductive tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.
2. The memory array of claim 1 wherein the insulator-material bodies comprise an oxide.
3. The memory array of claim 1 wherein the conductive material is directly against the insulator-material bodies.
4. The memory array of claim 1 wherein the insulator-material bodies do not laterally project into space between immediately-adjacent of the laterally-spaced memory block.
5. The memory array of claim 4 wherein the conductive material completely horizontally surrounds individual peripheries of the insulator-material bodies.
6. The memory array of claim 5 wherein the conductive material is directly against the insulator-material bodies.
7. The memory array of claim 1 wherein the conductive material does not completely horizontally surround individual peripheries of the insulator-material bodies.
8. The memory array of claim 7 wherein the conductive material horizontally covers a majority of the individual peripheries.
9. The memory array of claim 8 wherein the conductive material horizontally covers at least 75% of the individual peripheries.
10. The memory array of claim 9 wherein the conductive material is directly against the insulator-material bodies.
11. The memory array of claim 7 wherein the insulator-material bodies individually span completely across space between immediately-adjacent of the laterally-spaced memory-block regions in a finished circuitry construction.
12. The memory array of claim 1 wherein the lowest conductive tier is thicker than the conductive tiers there-above.
13. The memory array of claim 1 wherein a lowest surface of the channel material of the channel-material strings is not directly against any of the conductor material of the conductor tier.
14. The memory array of claim 1 wherein the conductive material in the lowest conductive tier is directly against a sidewall of the channel material of the channel-material strings.
15. The memory array of claim 1 wherein the conductive material in the lowest conductive tier is directly against an uppermost surface of the conductor material of the conductor tier.