Granted Patent B2

US 12,229,661 · App. 18/510,784 · Granted Feb 18, 2025

Inventors: Takahiko Ishizu (Sagamihara, JP); Takayuki Ikeda (Atsugi, JP); Atsuo Isobe (Isehara, JP); Atsushi Miyaguchi (Hadano, JP); Shunpei Yamazaki (Setagaya, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G06N3/065G06F1/3243G06F7/5443G06T1/20

Abstract

Claims (56)

1. An arithmetic device comprising:

a first arithmetic portion; and

a second arithmetic portion,

wherein the first arithmetic portion comprises a first central processing unit (CPU) core and a second CPU core,

wherein the second arithmetic portion comprises a first graphics processing unit (GPU) core and a second GPU core,

wherein the first CPU core and the second CPU core each are configured to perform power gating,

wherein the first CPU core and the second CPU core each comprise a first data retention circuit,

wherein the first GPU core comprises a second data retention circuit configured to retain an analog value and read out the analog value as digital data of two or more bits,

wherein the second GPU core comprises a third data retention circuit configured to retain a digital value and read out the digital value as digital data of one bit,

wherein the first to third data retention circuits each comprise a first transistor, a second transistor, and a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to the capacitor and a gate of the second transistor, and

wherein a channel formation region of the first transistor comprises an oxide semiconductor.

2. An arithmetic device comprising:

a first arithmetic portion; and

a second arithmetic portion,

wherein the first arithmetic portion comprises a plurality of central processing unit (CPU) cores,

wherein the second arithmetic portion comprises a plurality of graphics processing unit (GPU) cores,

wherein a first CPU core of the plurality of CPU cores and a second CPU core of the plurality of CPU cores each are configured to perform power gating,

wherein the first CPU core of the plurality of CPU cores and the second CPU core of the plurality of CPU cores each comprise a first data retention circuit,

wherein a first GPU core of the plurality of GPU cores comprises a second data retention circuit configured to retain an analog value and read out the analog value as digital data of two or more bits,

wherein a second GPU core of the plurality of GPU cores comprises a third data retention circuit configured to retain a digital value and read out the digital value as digital data of one bit,

wherein at least one of the first to third data retention circuits comprises a first transistor, a second transistor, and a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor and a gate of the second transistor, and

wherein a channel formation region of the first transistor comprises an oxide semiconductor.

3. An arithmetic device comprising:

a first arithmetic portion; and

a second arithmetic portion,

wherein the first arithmetic portion comprises a plurality of central processing unit (CPU) cores,

wherein the second arithmetic portion comprises a plurality of graphics processing unit (GPU) cores,

wherein a first CPU core of the plurality of CPU cores and a second CPU core of the plurality of CPU cores each are configured to perform power gating,

wherein the first CPU core of the plurality of CPU cores and the second CPU core of the plurality of CPU cores each comprise a first data retention circuit,

wherein a first GPU core of the plurality of GPU cores comprises a second data retention circuit configured to retain an analog value and read out the analog value as digital data of two or more bits,

wherein a second GPU core of the plurality of GPU cores comprises a third data retention circuit configured to retain a digital value and read out the digital value as digital data of one bit,

wherein the first to third data retention circuits each comprise a first transistor, a second transistor, and a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor and a gate of the second transistor,

wherein a channel formation region of the first transistor comprises an oxide semiconductor,

wherein the first data retention circuit is configured to retain data even when a supply of a power supply voltage is stopped,

wherein the arithmetic device is configured to bring one of the first CPU core of the plurality of CPU cores and the second CPU core of the plurality of CPU cores into a power gating state while the other of the first CPU core of the plurality of CPU cores and the second CPU core of the plurality of CPU cores remains in a state of executing processing, and

wherein the oxide semiconductor comprises at least one of Indium (In), Gallium (Ga), and Zinc (Zn).

4. An arithmetic device comprising:

a first arithmetic portion; and

a second arithmetic portion,

wherein the first arithmetic portion comprises a first central processing unit (CPU) core and a second CPU core,

wherein the second arithmetic portion comprises a first graphics processing unit (GPU) core and a second GPU core,

wherein the first CPU core and the second CPU core each are configured to perform power gating, and

wherein the first GPU core comprises a data retention circuit configured to retain an analog value and read out the analog value as digital data of two or more bits.

5. An integrated circuit comprising:

a digital-to-analog converter;

a plurality of product-sum operation circuit arrays; and

a gate driver,

wherein the digital-to-analog converter converts data corresponding to a weight coefficient into analog data,

wherein the gate driver is configured to control writing of the analog data into the plurality of product-sum operation circuit arrays,

wherein one of the plurality of product-sum operation circuit arrays comprises a multiplier circuit,

wherein the multiplier circuit comprises a first transistor, a second transistor, and a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor and a gate of the second transistor, and

wherein a channel formation region of the first transistor comprises an oxide semiconductor.

Priority Claims (3)

Continuity (3)

References Cited (42)