Nonvolatile memory device
A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.
1. A nonvolatile memory device, comprising:
a mold structure that includes a plurality of word lines stacked on a substrate and first, second, and third string selection lines sequentially stacked on the plurality of word lines;
a plurality of channel structures that penetrates the mold structure and is connected to the substrate;
a first cutting region that cuts the mold structure;
a second cutting region that is spaced apart from the first cutting region in a first direction parallel to an upper surface of the substrate and that cuts the mold structure, the first and second cutting regions extending in a second direction intersecting the first direction, the first and second cutting regions being immediately adjacent to each other;
first, second and third cutting lines that extend in the second direction and cut at least one of the first, second and third string selection lines between the first cutting region and the second cutting region; and
a bit line on the mold structure extending in the first direction,
wherein the channel structures include first to fourth channel structures sequentially arranged in the first direction between the first cutting region and the second cutting region and electrically connected to the bit line.
2. The nonvolatile memory device as claimed in claim 1 , wherein:
the first channel structure is between the first cutting region and the first cutting line in the first direction,
the second channel structure is between the first cutting line and the third cutting line in the first direction,
the third channel structure is between the third cutting line and the second cutting line in the first direction, and
the fourth channel structure is between the second cutting line and the second cutting region in the first direction.
3. The nonvolatile memory device as claimed in claim 1 , further comprising a plurality of dummy channel structures that is spaced apart from the channel structures, penetrates the mold structure, and intersects each word line of the plurality of word lines.
4. The nonvolatile memory device as claimed in claim 3 , wherein the plurality of dummy channel structures includes:
a first dummy channel structure that crosses the first cutting line,
a second dummy channel structure that crosses the third cutting line, and
a third dummy channel structure that crosses the second cutting line.
5. The nonvolatile memory device as claimed in claim 3 , wherein the channel structures are arranged along the first direction in a zigzag shape and the dummy channel structures are arranged along the first direction in a zigzag shape.
6. The nonvolatile memory device as claimed in claim 3 , wherein the dummy channel structures are not connected to the bit line.
7. The nonvolatile memory device as claimed in claim 3 , wherein:
the dummy channel structures has a pillar shape extending in a third direction intersecting the first direction and the second direction, and
each of the dummy channel structures includes:
a semiconductor pattern that penetrates the mold structure and is connected to the substrate, and
an information storage film between the semiconductor pattern and each word line of the plurality of word lines.
8. The nonvolatile memory device as claimed in claim 1 , wherein the third cutting line is between the first cutting line and the second cutting line with respect to a plan view.
9. The nonvolatile memory device as claimed in claim 1 , wherein:
the first cutting line cuts the first string selection line,
the second cutting line cuts the second string selection line, and
the third cutting line cuts the third string selection line.
10. The nonvolatile memory device as claimed in claim 1 , wherein a width of each of the first, second, and third cutting lines in the first direction increases in a third direction extending away from the substrate.
11. A nonvolatile memory device, comprising:
a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate;
a plurality of channel structures that penetrates the mold structure and intersects the plurality of gate electrodes, wherein each gate electrode of the plurality of gate electrodes is intersected by at least one channel structure of the plurality of channel structures;
a first cutting region that cuts each gate electrode of the plurality of gate electrodes;
a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each gate electrode of the plurality of gate electrodes;
a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region;
a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region;
a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region; and
a plurality of bit lines connected to the plurality of channel structures and extending in the first direction,
wherein:
the first cutting line is spaced apart from the first cutting region by a first distance and is spaced apart from the second cutting region by a second distance,
the second cutting line is spaced apart from the first cutting region by a third distance and is spaced apart from the second cutting region by a fourth distance,
the third cutting line is spaced apart from the first cutting region by a fifth distance and is spaced apart from the second cutting region by a sixth distance,
a first difference between the first distance and the second distance is greater than a third difference between the fifth distance and the sixth distance,
a second difference between the third distance and the fourth distance is greater than the third difference, and
the plurality of bit lines includes first to fourth bit lines each connected to four channel structures of the plurality of channel structures.
12. The nonvolatile memory device as claimed in claim 11 , wherein:
the plurality of channel structures includes first to sixteenth channel structures,
the first bit line is connected to the first to fourth channel structures,
the second bit line is connected to the fifth to eighth channel structures and is spaced apart from the first bit line in a second direction,
the third bit line is connected to the ninth to twelfth channel structures and is spaced apart from the second bit line in the second direction, and
the fourth bit line is connected to the thirteenth to sixteenth channel structures and is spaced apart from the third bit line in the second direction.
13. The nonvolatile memory device as claimed in claim 11 , wherein the channel structures include first to fourth channel structures sequentially arranged in the first direction between the first cutting region and the second cutting region, and wherein:
the first channel structure is between the first cutting region and the first cutting line in the first direction,
the second channel structure is between the first cutting line and the third cutting line in the first direction,
the third channel structure is between the third cutting line and the second cutting line in the first direction, and
the fourth channel structure is between the second cutting line and the second cutting region in the first direction.
14. The nonvolatile memory device as claimed in claim 11 , further comprising a plurality of dummy channel structures, wherein each dummy channel structure of the plurality of dummy channel structures is spaced apart from the channel structures, penetrates the mold structure, and intersects at least one gate electrode of the plurality of gate electrodes, and wherein each gate electrode of the plurality of gate electrodes is intersected by at least one dummy channel structure of the plurality of dummy channel structures.
15. The nonvolatile memory device as claimed in claim 14 , wherein a bit line contact is not formed on the plurality of dummy channel structures.
16. The nonvolatile memory device as claimed in claim 11 , wherein the third string selection line is an uppermost gate electrode among the plurality of gate electrodes relative to the substrate.
17. A nonvolatile memory device, comprising:
a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate;
channel structures that penetrate the mold structure and intersect each gate electrode of the plurality of gate electrodes;
a first cutting region that cuts each gate electrode of the plurality of gate electrodes;
a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each gate electrode is of the plurality of gate electrodes;
a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region;
a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and
a third cutting line that cuts a third string selection line between the first cutting region and the second cutting region,
wherein:
the first cutting line is spaced apart from the first cutting region by a first distance and is spaced apart from the second cutting region by a second distance greater than the first distance,
the second cutting line is spaced apart from the first cutting region by a third distance and is spaced apart from the second cutting region by a fourth distance smaller than the third distance,
the third cutting line is spaced apart from the first cutting region by a fifth distance greater than the first distance and greater than the fourth distance,
the third cutting line is spaced apart from the second cutting region by a sixth distance greater than the first distance and greater than the fourth distance,
the channel structures include first to fourth channel structures sequentially arranged in the first direction between the first cutting region and the second cutting region and electrically connected to each other.
18. The nonvolatile memory device as claimed in claim 17 , wherein:
the first channel structure is between the first cutting region and the first cutting line in the first direction,
the second channel structure is between the first cutting line and the third cutting line in the first direction,
the third channel structure is between the third cutting line and the second cutting line in the first direction, and
the fourth channel structure is between the second cutting line and the second cutting region in the first direction.
19. The nonvolatile memory device as claimed in claim 17 , further comprising a bit line on the mold structure and electrically connected to the channel structures,
wherein the bit line extends in the first direction.
20. The nonvolatile memory device as claimed in claim 17 , wherein the first, second, and third cutting lines do not overlap each other with respect to a plan view.