Integrated assemblies and methods of forming integrated assemblies
Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.
1. A method of forming an integrated assembly, comprising:
forming a construction to include a slit which extends through a stack of alternating insulative levels and conductive levels;
forming a slit extending from an upper surface over the stack and through the stack;
forming a layer of first material within the slit to partially fill the slit, a cavity remaining within the partially-filled slit, the layer of first material extending across a base of the slit and having inner and outer sidewalls extending to the upper surface of the stack;
forming an oxide along interior sidewalls of the cavity and retaining an open area within the cavity;
prior to deposition any additional material within the open area, widening an upper region of the open area of the cavity while retaining the height of the layer of first material and retaining the first material along the base of the slit; and
after the widening, filling the cavity with a second material.
2. The method of claim 1 wherein the widening comprises one or both of chemical-mechanical polishing and dry etching.
3. The method of claim 1 wherein the first and second materials include one or more of semiconductor material, metal, silicon dioxide and silicon nitride.
4. The method of claim 1 wherein the first and second materials include one or more of Ge, Si, W, SiO and SiN, where the chemical formulas indicate primary compositions rather than specific stoichiometries.
5. The method of claim 1 wherein the second material is a different composition than the first material.
6. The method of claim 1 wherein the second material is a different density than the first material.
7. The method of claim 1 wherein the second material is a same composition as the first material.
8. The method of claim 1 wherein an outer periphery of the cavity includes a surface of the first material, and further comprising oxidizing the surface of the first material prior to filling the cavity with the second material.
9. The method of claim 8 wherein the first material comprises one or more of Si, Ge and W.
10. The method of claim 1 wherein the slit is between a first memory-block-region and a second memory-block-region.
11. The method of claim 1 wherein the second material overfills the cavity; and further comprising utilizing chemical-mechanical polishing to remove excess second material from outside of the cavity.
12. A method of forming an integrated assembly, comprising:
forming a construction to include a slit between a first memory-block-region and a second memory-block-region; the slit having first and second opposing sidewalls; the slit having a bottom which is along a conductive source structure;
forming first and second sidewall spacers along the first and second sidewalls of the slit to narrow the slit;
after forming the first and second sidewall spacers, forming a first material within the narrowed slit to partially fill the narrowed slit, a cavity remaining within the partially-filled narrowed slit; the first material within the narrowed slit being configured as a container shape having a height extending the entirety of a depth of the slit and having a bottom region directly against the conductive source structure; the cavity being an interior region of the container shape with a base of the bottom region of the container shape extending along an entirety of a bottom of the cavity, the cavity having sidewalls consisting of a single material;
prior to depositing any material within the cavity, widening an upper region of the cavity while retaining the height of the first material; and
after the widening, forming a second material within the cavity.
13. The method of claim 12 wherein an outer periphery of the cavity includes a surface of the first material, and further comprising oxidizing the surface of the first material prior to forming the second material within the cavity.
14. The method of claim 13 wherein the first material comprises one or more of Si, Ge and W.
15. The method of claim 12 wherein the widening comprises one or both of chemical-mechanical polishing and dry etching.
16. The method of claim 12 wherein the first and second materials include one or more of semiconductor material, metal, silicon dioxide and silicon nitride.
17. The method of claim 12 wherein the first and second materials include one or more of Ge, Si, W, SiO and SiN, where the chemical formulas indicate primary compositions rather than specific stoichiometries.
18. The method of claim 12 wherein the second material is a different composition than the first material.
19. The method of claim 12 wherein the second material is a different density than the first material.
20. The method of claim 12 wherein the second material is a same composition as the first material.