Granted Patent B2

US 12,253,944 · App. 17/908,879 · Granted Mar 18, 2025

Inventors: Steven Milburn (Wayland, MA); Nirmal Nepal (Wayland, MA)

Assignee: Dover Microsystems, Inc.

G06F12/0802G06F12/1009G06F21/79

Abstract

Claims (157)

1. A computer-implemented method for caching metadata, the method comprising acts of:

in response to an access request comprising an application memory address, determining whether the application memory address matches an entry of at least one cache;

in response to determining that the application memory address does not match any entry of the at least one cache:

using the application memory address to retrieve application data;

mapping the application memory address to at least one metadata memory address; and

using the at least one metadata memory address to retrieve metadata corresponding to the application memory address; and

creating an entry in the at least one cache, wherein:

the entry is indexed by the application memory address; and

the entry stores both the application data retrieved using the application memory address, and the corresponding metadata retrieved using the at least one metadata memory address.

2. The method of claim 1 , wherein:

the application data is retrieved from at least one application memory;

the corresponding metadata is retrieved from at least one metadata memory; and

the at least one application memory and the at least one metadata memory are separate physical memories, or disjoint portions of a same physical memory.

3. The method of claim 1 , wherein:

mapping the application memory address to at least one metadata memory address comprises using the application memory address to look up a tag map table; and

the at least one metadata memory address is returned by the tag map table.

4. The method of claim 1 , wherein:

the access request is received from a fetch stage of a processor pipeline;

the application memory address comprises an instruction address;

the at least one cache comprises an instruction cache; and

the method further comprises acts of:

returning the application data to the fetch stage as an instruction to be executed by the processor pipeline; and

providing the metadata corresponding to the instruction address to a metadata processing system.

5. The method of claim 1 , wherein:

the access request is received from an execute stage of a processor pipeline;

the application memory address comprises a target address of a load instruction;

the at least one cache comprises a data cache; and

the method further comprises acts of:

returning the application data to the execute stage as data loaded from the target address of the load instruction; and

providing the metadata corresponding to the target address to a metadata processing system.

6. The method of claim 5 , wherein:

the metadata retrieved using the at least one metadata memory address comprises first metadata corresponding to the application memory address; and

the method further comprising acts of:

receiving, from the metadata processing system, second metadata corresponding to the application memory address, the second metadata resulting from the metadata processing system checking the load instruction in accordance with one or more policies; and

updating the entry indexed by the application memory address, comprising writing into the entry the second metadata received from the metadata processing system, replacing the first metadata retrieved using the at least one metadata memory address.

7. The method of claim 1 , wherein:

the application data retrieved using the application memory address comprises first application data;

the application memory address comprises a target address of a store instruction;

the access request further comprises second application data, the second application data to be stored by the store instruction;

the at least one cache comprises a data cache; and

the method further comprises acts of:

holding the application data to be stored in a buffer;

providing the metadata corresponding to the application memory address to a metadata processing system; and

in response to receiving, from the metadata processing system, an indication to allow the store instruction:

releasing the second application data from the buffer; and

writing the second application data into the entry indexed by the application memory address, replacing the first application data.

8. The method of claim 7 , wherein:

the metadata provided to the metadata processing system comprises first metadata corresponding to the application memory address;

the indication from the metadata processing system to allow the store instruction comprises second metadata corresponding to the application memory address, the second metadata resulting from the metadata processing system checking the store instruction in accordance with one or more policies; and

the method further comprising an act of:

writing the second metadata into the entry indexed by the application memory address, replacing the first metadata.

9. The method of claim 1 , wherein:

the application memory address comprises a virtual address;

determining whether the application memory address matches an entry of at least one cache comprises:

matching the virtual address to a page table entry storing address translation information; and

using the address translation information from the page table entry to map the virtual address to a physical address;

the page table entry further stores metadata mapping information; and

the application memory address is mapped to the at least one metadata memory address using the metadata mapping information from the page table entry.

10. The method of claim 9 , wherein:

the metadata mapping information comprises an index identifying an entry in a tag map table; and

the at least one metadata memory address is retrieved from the entry in the tag map table.

11. The method of claim 1 , wherein:

the application memory address comprises a first application memory address;

the at least one metadata memory address comprises at least one first metadata memory address;

the method further comprising acts of:

in response to determining that the application memory address does not match an entry of the at least one cache, determining whether any cache line matching one or more index bits of the application memory address is available;

in response to determining that no cache line matching the one or more index bits of the application memory address is available, selecting, for eviction, a cache line matching the one or more index bits of the application memory address; and

evicting the selected cache line, comprising:

determining a second application memory address, the second application memory address being cached at the selected cache line;

mapping the second application memory address to at least one second metadata memory address;

using the second application memory address to write application data from the selected cache line to an application memory; and

using the at least one second metadata memory address to write metadata from the selected cache line to a metadata memory; and

the entry indexed by the application memory address is created at the selected cache line after the selected cache line has been evicted.

12. A system comprising circuitry and/or one or more processors programmed by executable instructions, wherein the circuitry and/or the one or more programmed processors are configured to:

in response to an access request comprising an application memory address, determine whether the application memory address matches an entry of at least one cache;

in response to determining that the application memory address does not match any entry of the at least one cache:

use the application memory address to retrieve application data;

map the application memory address to at least one metadata memory address; and

use the at least one metadata memory address to retrieve metadata corresponding to the application memory address; and

create an entry in the at least one cache, wherein:

the entry is indexed by the application memory address; and

the entry stores both the application data retrieved using the application memory address, and the corresponding metadata retrieved using the at least one metadata memory address.

13. The system of claim 12 , wherein:

the application data is retrieved from at least one application memory;

the corresponding metadata is retrieved from at least one metadata memory; and

the at least one application memory and the at least one metadata memory are separate physical memories, or disjoint portions of a same physical memory.

14. The system of claim 12 , wherein:

the circuitry and/or the one or more programmed processors are configured to map the application memory address to at least one metadata memory address at least in part by using the application memory address to look up a tag map table; and

the at least one metadata memory address is returned by the tag map table.

15. The system of claim 12 , wherein:

the access request is received from a fetch stage of a processor pipeline;

the application memory address comprises an instruction address;

the at least one cache comprises an instruction cache; and

the circuitry and/or the one or more programmed processors are further configured to:

return the application data to the fetch stage as an instruction to be executed by the processor pipeline; and

provide the metadata corresponding to the instruction address to a metadata processing system.

16. The system of claim 12 , wherein:

the access request is received from an execute stage of a processor pipeline;

the application memory address comprises a target address of a load instruction;

the at least one cache comprises a data cache; and

the circuitry and/or the one or more programmed processors are further configured to:

return the application data to the execute stage as data loaded from the target address of the load instruction; and

provide the metadata corresponding to the target address to a metadata processing system.

17. The system of claim 16 , wherein:

the metadata retrieved using the at least one metadata memory address comprises first metadata corresponding to the application memory address; and

the circuitry and/or the one or more programmed processors are further configured to:

receive, from the metadata processing system, second metadata corresponding to the application memory address, the second metadata resulting from the metadata processing system checking the load instruction in accordance with one or more policies; and

update the entry indexed by the application memory address, at least in part by writing into the entry the second metadata received from the metadata processing system, replacing the first metadata retrieved using the at least one metadata memory address.

18. The system of claim 12 , wherein:

the application data retrieved using the application memory address comprises first application data;

the application memory address comprises a target address of a store instruction;

the access request further comprises second application data, the second application data to be stored by the store instruction;

the at least one cache comprises a data cache; and

the circuitry and/or the one or more programmed processors are further configured to:

hold the application data to be stored in a buffer;

provide the metadata corresponding to the application memory address to a metadata processing system; and

in response to receiving, from the metadata processing system, an indication to allow the store instruction:

release the second application data from the buffer; and

write the second application data into the entry indexed by the application memory address, replacing the first application data.

19. The system of claim 18 , wherein:

the metadata provided to the metadata processing system comprises first metadata corresponding to the application memory address;

the indication from the metadata processing system to allow the store instruction comprises second metadata corresponding to the application memory address, the second metadata resulting from the metadata processing system checking the store instruction in accordance with one or more policies; and

the circuitry and/or the one or more programmed processors are further configured to:

write the second metadata into the entry indexed by the application memory address, replacing the first metadata.

20. The system of claim 12 , wherein:

the application memory address comprises a virtual address;

the circuitry and/or the one or more programmed processors are configured to determine whether the application memory address matches an entry of at least one cache at least in part by:

matching the virtual address to a page table entry storing address translation information; and

using the address translation information from the page table entry to map the virtual address to a physical address;

the page table entry further stores metadata mapping information; and

the application memory address is mapped to the at least one metadata memory address using the metadata mapping information from the page table entry.

21. The system of claim 20 , wherein:

the metadata mapping information comprises an index identifying an entry in a tag map table; and

the at least one metadata memory address is retrieved from the entry in the tag map table.

22. The system of claim 12 , wherein:

the application memory address comprises a first application memory address;

the at least one metadata memory address comprises at least one first metadata memory address;

the circuitry and/or the one or more programmed processors are further configured to:

in response to determining that the application memory address does not match an entry of the at least one cache, determine whether any cache line matching one or more index bits of the application memory address is available;

in response to determining that no cache line matching the one or more index bits of the application memory address is available, select, for eviction, a cache line matching the one or more index bits of the application memory address; and

evict the selected cache line, at least in part by:

determining a second application memory address, the second application memory address being cached at the selected cache line;

mapping the second application memory address to at least one second metadata memory address;

using the second application memory address to write application data from the selected cache line to an application memory; and

using the at least one second metadata memory address to write metadata from the selected cache line to a metadata memory; and

the entry indexed by the application memory address is created at the selected cache line after the selected cache line has been evicted.

23. At least one non-transitory computer-readable medium having stored thereon at least one hardware description for circuitry, wherein the circuitry is configured to:

in response to an access request comprising an application memory address, determine whether the application memory address matches an entry of at least one cache;

in response to determining that the application memory address does not match any entry of the at least one cache:

use the application memory address to retrieve application data;

map the application memory address to at least one metadata memory address; and

use the at least one metadata memory address to retrieve metadata corresponding to the application memory address; and

create an entry in the at least one cache, wherein:

the entry is indexed by the application memory address; and

the entry stores both the application data retrieved using the application memory address, and the corresponding metadata retrieved using the at least one metadata memory address.

24. The at least one non-transitory computer-readable medium of claim 23 , wherein the at least one hardware description is in an encrypted form.

25. The at least one non-transitory computer-readable medium of claim 23 , wherein the at least one hardware description, when synthesized, produces at least one netlist for the circuitry.

Assignments (1)

Continuity (2)

References Cited (400)