Semiconductor device and power converter
The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.
1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a first semiconductor region of the first conductivity type selectively in an upper layer of the first semiconductor layer;
a second semiconductor region of a second conductivity type in the upper layer of the first semiconductor layer and in contact with the first semiconductor region;
a third semiconductor region of the second conductivity type on bottom surfaces of the first and second semiconductor regions;
a plurality of gate trenches that penetrate the first and third semiconductor regions in a thickness direction of the first and third semiconductor regions, the plurality of gate trenches each comprising a bottom surface reaching an inside of the first semiconductor layer, the plurality of gate trenches being in a form of stripes and extending in one direction in a plan view and not in contact with each other at intervals;
a plurality of field-reducing regions of the second conductivity type respectively on the bottom surfaces of corresponding ones of the plurality of gate trenches;
an interlayer insulating film comprising contact openings above the first and second semiconductor regions;
a plurality of connection layers in the first semiconductor layer at intervals and each in contact with at least one sidewall of a corresponding one of the plurality of gate trenches in a second direction perpendicular to a first direction parallel with a direction in which the plurality of gate trenches extend,
the plurality of connection layers respectively electrically connects a corresponding one of the field-reducing regions to the third semiconductor region;
a first main electrode over the interlayer insulating film and filled in the contact openings; and
a second main electrode on a main surface of the first semiconductor layer, the main surface being opposite from where the first main electrode is disposed,
wherein the first semiconductor layer has an off-angle greater than 0 degrees,
the first direction is parallel with an off-direction, and
the plurality of connection layers are spaced from each other in the first direction.
2. The semiconductor device according to claim 1 , wherein
the first semiconductor layer comprises a silicon-carbide layer,
the first semiconductor layer has an off-angle greater than 0 degrees in a <11-20> direction, and
the plurality of gate trenches each comprise a sidewall surface comprising a (1-100) plane or (-1100) plane.
3. The semiconductor device according to claim 1 , wherein
each of the plurality of connection layers extends in the second direction from the sidewall of the corresponding one of the plurality of gate trenches, and
the plurality of connection layers are shorter in the second direction than a length between the plurality of gate trenches adjacent to each other.
4. The semiconductor device according to claim 1 , wherein the plurality of connection layer each include:
a first connection layer in contact with the corresponding one of the plurality of gate trenches, and
a second connection layer farther from the corresponding one of the plurality of gate trenches than the first connection layer,
wherein the first connection layer has an impurity concentration higher than an impurity concentration of the second connection layer.
5. The semiconductor device according to claim 1 , wherein the plurality of connection layers each has an impurity concentration of 1×10 17 cm −3 or more and 5×10 19 cm −3 or less.
6. The semiconductor device according to claim 1 , wherein the plurality of connection layers each has a length of 0.3 μm or more in a thickness direction of the first semiconductor layer.
7. The semiconductor device according to claim 1 , wherein the plurality of connection layers each include:
a first connection layer in contact with the corresponding one of the plurality of gate trenches, and
a second connection layer farther from the corresponding one of the plurality of gate trenches than the first connection layer,
wherein the first and second connection layers are of the second conductivity type.
8. The semiconductor device according to claim 1 , wherein the plurality of connection layers each include:
a first connection layer in contact with the corresponding one of the plurality of gate trenches, and
a second connection layer farther from the corresponding one of the plurality of gate trenches than the first connection layer, wherein
the first connection layer is of the first conductivity type, and
the second connection layer is of the second conductivity type.
9. The semiconductor device according to claim 1 , wherein each of the plurality of connection layers has a length in a thickness direction of the first semiconductor layer that decreases along with distance in the second direction from the sidewall of the corresponding one of the plurality of gate trenches.
10. The semiconductor device according to claim 1 , wherein the plurality of connection layers are on only one of the side walls of the corresponding one of the plurality of gate trenches in the second direction.
11. The semiconductor device according to claim 1 , wherein the plurality of connection layers are alternately on one of the sidewalls and the other sidewall of the corresponding one of the plurality of gate trenches in the second direction.
12. The semiconductor device according to claim 1 , wherein the plurality of connection layers are in contact with the second semiconductor region.
13. The semiconductor device according to claim 1 , further comprising:
a current spreading region of the first conductivity type in the first semiconductor layer, the current spreading region being in contact with each of the plurality of connection layers and the field-reducing region,
wherein the current spreading region has an impurity concentration higher than that of the first semiconductor layer.
14. The semiconductor device according to claim 1 , further comprising a second semiconductor layer of the first conductivity type on a bottom surface of the third semiconductor region.
15. The semiconductor device according to claim 1 , wherein the plurality of gate trenches include:
a first gate trench comprising an inner-wall surface covered with a gate insulating film, the first gate trench being filled with a gate electrode, and
a second gate trench comprising an inner-wall surface covered with a Schottky electrode, the second gate trench being filled with the first main electrode, and the first gate trench comprises an upper portion covered with the interlayer insulating film.
16. The semiconductor device according to claim 1 , wherein
the plurality of connection layers are of the second conductivity type,
each of the plurality of connection layers and the field-reducing region forms a pillar of the second conductivity type,
the first semiconductor layer between the pillars of the second conductivity type adjacent to each other forms a pillar of the first conductivity type, and
the pillar of the first conductivity type and the pillar of the second conductivity type form a super-junction structure.
17. The semiconductor device according to claim 16 , wherein each of the plurality of connection layers is in contact with a part of a side surface of the field-reducing region.
18. The semiconductor device according to claim 1 , further comprising a third semiconductor layer of the second conductivity type between the second main electrode and the first semiconductor layer.
19. The semiconductor device according to claim 1 , wherein the contact openings are uniform in length in at least the second direction, in an active region where the plurality of gate trenches are arranged.
20. A power converter comprising:
a main conversion circuit comprising the semiconductor device according to claim 1 , the main conversion circuit being configured to convert and then output received power;
a drive circuit configured to output a drive signal for driving the semiconductor device, to the semiconductor device; and
a control circuit configured to output a control signal for controlling the drive circuit, to the drive circuit.